Re: [U-Boot] [PATCH] powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs

On 01/06/2015 10:44 PM, Shaveta Leekha wrote:

The code provides framework for heterogeneous multicore chips based on StarCore and Power Architecture which are chasis-2 compliant, like B4860 and B4420

It will make u-boot recognize all non-ppc cores and peripherals like SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs. Example boot logs of B4420: Clock Configuration: CPU0:1600 MHz, CPU1:1600 MHz, DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, CCB:666.667 MHz, DDR:800 MHz (1600 MT/s data rate) (Asynchronous), IFC:166.667 MHz CPRI:600 MHz MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz FMAN1: 666.667 MHz QMAN: 333.333 MHz

Top level changes include: (1) Top level CONFIG to identify HETEROGENUOUS clusters (2) CONFIGS for SC3900/DSP components (3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO" updated for dsp cores and other components (3) APIs to get DSP num cores and their Mask like: cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC (5) Code to fetch and print SC cores and other heterogenous device's frequencies (6) README added for the same

Signed-off-by: Shaveta Leekha shaveta@freescale.com

arch/powerpc/cpu/mpc85xx/cpu.c | 25 +++++ arch/powerpc/cpu/mpc85xx/speed.c | 136 +++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc8xxx/cpu.c | 89 +++++++++++++++++++- arch/powerpc/include/asm/config_mpc85xx.h | 14 +++- arch/powerpc/include/asm/processor.h | 5 + doc/README.Heterogeneous-SoCs | 105 ++++++++++++++++++++++ include/common.h | 2 + include/e500.h | 11 +++ 8 files changed, 384 insertions(+), 3 deletions(-) create mode 100644 doc/README.Heterogeneous-SoCs

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 3d6ec84..69ab14c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -71,7 +71,9 @@ int checkcpu (void) #endif /* CONFIG_FSL_CORENET */

unsigned int i, core, nr_cores = cpu_numcores();

• unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores(); u32 mask = cpu_mask();

• u32 dsp_mask = cpu_dsp_mask();

  svr = get_svr(); major = SVR_MAJ(svr);

@@ -166,6 +168,16 @@ int checkcpu (void) printf("CPU%d:%-4s MHz, ", core, strmhz(buf1, sysinfo.freq_processor[core])); }

+#ifdef CONFIG_HETROGENOUS_CLUSTERS

• for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {

• if (!(j & 3))
  

• 	printf("\n       ");
  

• printf("DSP CPU%d:%-4s MHz, ", j,
  

•        strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
  

• }

+#endif

• printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus)); printf("\n");

@@ -224,6 +236,19 @@ int checkcpu (void) printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe)); #endif

+#if defined(CONFIG_SYS_CPRI)

• printf(" ");
• printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));

+#endif

+#if defined(CONFIG_SYS_MAPLE)

• printf("\n ");
• printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
• printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
• printf("MAPLE-eTVPE:%-4s MHz\n",

•       strmhz(buf1, sysinfo.freq_maple_etvpe));
  

+#endif

#ifdef CONFIG_SYS_DPAA_FMAN for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 7e69873..43e23a5 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -35,6 +35,7 @@ void get_sys_info(sys_info_t *sys_info) volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); unsigned int cpu; #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2

• unsigned int dsp_cpu; int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;

#endif __maybe_unused u32 svr; @@ -69,6 +70,7 @@ void get_sys_info(sys_info_t *sys_info) [14] = 4, /* CC4 PPL / 4 */ }; uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];

• uint rcw_tmp1, rcw_tmp2;

#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) uint rcw_tmp; #endif @@ -157,6 +159,7 @@ void get_sys_info(sys_info_t *sys_info) else freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; }

#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* * As per CHASSIS2 architeture total 12 clusters are posible and @@ -181,6 +184,18 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_processor[cpu] = freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; }

• for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {

• int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
  

• u32 c_pll_sel = (in_be32
  

• 		(&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
  

• 		& 0xf;
  

• u32 cplx_pll = core_cplx_PLL[c_pll_sel];
  

• cplx_pll += cc_group[dsp_cluster] - 1;
  

• sys_info->freq_processor_dsp[dsp_cpu] =
  

• 	 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
  

• }

Suggest you to add #ifdef for the above change. We don't need to increase the code size for other SoCs.

Please test u-boot for at least B4860 and T4240. You will see some compiling errors.

York