The current implementation of spl_board_init() is not correct, the MX8MM BootROM v1 does not support SDP load when re-entered from U-Boot SPL, it is up to U-Boot to perform the next stage load using its own internal CI gadget driver and SDP protocol implementation. Drop the spl_board_init() to let SPL continue with normal load in case the SDP support is enabled.
Signed-off-by: Marek Vasut marex@denx.de --- Cc: Fabio Estevam festevam@denx.de Cc: Peng Fan peng.fan@nxp.com Cc: Stefano Babic sbabic@denx.de Cc: Teresa Remmet t.remmet@phytec.de --- board/phytec/phycore_imx8mm/spl.c | 10 ---------- configs/phycore-imx8mm_defconfig | 1 - 2 files changed, 11 deletions(-)
diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index d87ab6d4497..1bae9b1170d 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -42,16 +42,6 @@ static void spl_dram_init(void) ddr_init(&dram_timing); }
-void spl_board_init(void) -{ - /* Serial download mode */ - if (is_usb_boot()) { - puts("Back to ROM, SDP\n"); - restore_boot_params(); - } - puts("Normal Boot\n"); -} - int board_fit_config_name_match(const char *name) { return 0; diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 9b8c09a73ab..e8d7905bb4a 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -30,7 +30,6 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 -CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK=0x920000 CONFIG_SYS_SPL_MALLOC=y