Marek Vasut marex@denx.de schrieb am Do., 3. Okt. 2019, 14:19:
On 10/3/19 1:40 PM, Marek Vasut wrote:
On 10/3/19 9:55 AM, Jagan Teki wrote:
On Thu, Oct 3, 2019 at 4:26 AM Marek Vasut wrote:
Convert the designware watchdog timer driver to DM and add DT probing support. Perform minor coding style clean up, like drop superfluous braces. These ought to be no functional change.
configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + drivers/watchdog/Kconfig | 14 ++-- drivers/watchdog/designware_wdt.c | 97 +++++++++++++++++++-------- 4 files changed, 77 insertions(+), 36 deletions(-)
fyi: this is already in ML [1] and yet to pick for next MW. let me know if you have any questions?
It's a pity I wasn't CCed on that patch.
That patch won't work for SoCFPGA, see my reply to Ley. We will need one which can do non-DM WDT in SPL, so I will be sending a V2 of this one which retains the common code and still supports HW_WATCHDOG in SPL and DM-WDT in U-Boot proper.
Oh, and the clock/reset stuff should be optional, since at least DM clock are not present on socfpga gen5 yet.
I'm working on that. Sadly, I haven't fou,d the time to finish it up since mid August, but I'm planning to do it in the upcoming merge window.
Regards, Simon