On Thu, Mar 11, 2021 at 9:50 PM Green Wan green.wan@sifive.com wrote:
Add dts support for fu740
The commit summary should mention both fu740 and HiFive Unmatched
Signed-off-by: Green Wan green.wan@sifive.com
arch/riscv/dts/Makefile | 1 + arch/riscv/dts/fu740-c000-u-boot.dtsi | 105 ++++++++ arch/riscv/dts/fu740-c000.dtsi | 329 ++++++++++++++++++++++++++ include/dt-bindings/clock/sifive-fu740-prci.h | 25 ++ include/dt-bindings/reset/sifive-fu740-prci.h | 19 ++ 5 files changed, 479 insertions(+) create mode 100644 arch/riscv/dts/fu740-c000-u-boot.dtsi create mode 100644 arch/riscv/dts/fu740-c000.dtsi create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h create mode 100644 include/dt-bindings/reset/sifive-fu740-prci.h
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 01331b0..2254e6b 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -2,6 +2,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb +dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi new file mode 100644 index 0000000..0115a44 --- /dev/null +++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/*
- (C) Copyright 2020-2021 SiFive, Inc
- */
+#include <dt-bindings/reset/sifive-fu740-prci.h>
+/ {
cpus {assigned-clocks = <&prci PRCI_CLK_COREPLL>;assigned-clock-rates = <1001000000>;u-boot,dm-spl;cpu0: cpu@0 {clocks = <&prci PRCI_CLK_COREPLL>;u-boot,dm-spl;status = "okay";cpu0_intc: interrupt-controller {u-boot,dm-spl;};};cpu1: cpu@1 {clocks = <&prci PRCI_CLK_COREPLL>;u-boot,dm-spl;cpu1_intc: interrupt-controller {u-boot,dm-spl;};};cpu2: cpu@2 {clocks = <&prci PRCI_CLK_COREPLL>;u-boot,dm-spl;cpu2_intc: interrupt-controller {u-boot,dm-spl;};};cpu3: cpu@3 {clocks = <&prci PRCI_CLK_COREPLL>;u-boot,dm-spl;cpu3_intc: interrupt-controller {u-boot,dm-spl;};};cpu4: cpu@4 {clocks = <&prci PRCI_CLK_COREPLL>;u-boot,dm-spl;cpu4_intc: interrupt-controller {u-boot,dm-spl;};};};soc {u-boot,dm-spl;clint: clint@2000000 {compatible = "riscv,clint0";interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7&cpu1_intc 3 &cpu1_intc 7&cpu2_intc 3 &cpu2_intc 7&cpu3_intc 3 &cpu3_intc 7&cpu4_intc 3 &cpu4_intc 7>;reg = <0x0 0x2000000 0x0 0x10000>;u-boot,dm-spl;};prci: clock-controller@10000000 {#reset-cells = <1>;resets = <&prci PRCI_RST_DDR_CTRL_N>,<&prci PRCI_RST_DDR_AXI_N>,<&prci PRCI_RST_DDR_AHB_N>,<&prci PRCI_RST_DDR_PHY_N>,<&prci PRCI_RST_GEMGXL_N>,<&prci PRCI_RST_CLTX_N>;reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb","ddr_phy", "gemgxl_reset", "cltx_reset";};dmc: dmc@100b0000 {compatible = "sifive,fu740-c000-ddr";reg = <0x0 0x100b0000 0x0 0x08000x0 0x100b2000 0x0 0x20000x0 0x100b8000 0x0 0x1000>;clocks = <&prci PRCI_CLK_DDRPLL>;clock-frequency = <933333324>;u-boot,dm-spl;};};+};
+&prci {
u-boot,dm-spl;+};
+&uart0 {
u-boot,dm-spl;+};
+&spi0 {
u-boot,dm-spl;+};
+ð0 {
assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;assigned-clock-rates = <125125000>;+};
+&ccache {
status = "okay";+}; diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi new file mode 100644 index 0000000..0325e51 --- /dev/null +++ b/arch/riscv/dts/fu740-c000.dtsi @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2021 SiFive, Inc */
+/dts-v1/;
+#include <dt-bindings/clock/sifive-fu740-prci.h> +#include <dt-bindings/reset/sifive-fu740-prci.h>
+/ {
#address-cells = <2>;#size-cells = <2>;compatible = "sifive,fu740-c000", "sifive,fu740";aliases {serial0 = &uart0;serial1 = &uart1;ethernet0 = ð0;};chosen {};cpus {#address-cells = <1>;#size-cells = <0>;cpu0: cpu@0 {compatible = "sifive,bullet0", "riscv";device_type = "cpu";i-cache-block-size = <64>;i-cache-sets = <128>;i-cache-size = <16384>;next-level-cache = <&ccache>;reg = <0x0>;riscv,isa = "rv64imac";status = "disabled";cpu0_intc: interrupt-controller {#interrupt-cells = <1>;compatible = "riscv,cpu-intc";interrupt-controller;};};cpu1: cpu@1 {compatible = "sifive,bullet0", "riscv";d-cache-block-size = <64>;d-cache-sets = <64>;d-cache-size = <32768>;d-tlb-sets = <1>;d-tlb-size = <40>;device_type = "cpu";i-cache-block-size = <64>;i-cache-sets = <128>;i-cache-size = <32768>;i-tlb-sets = <1>;i-tlb-size = <40>;mmu-type = "riscv,sv39";next-level-cache = <&ccache>;reg = <0x1>;riscv,isa = "rv64imafdc";tlb-split;cpu1_intc: interrupt-controller {#interrupt-cells = <1>;compatible = "riscv,cpu-intc";interrupt-controller;};};cpu2: cpu@2 {compatible = "sifive,bullet0", "riscv";d-cache-block-size = <64>;d-cache-sets = <64>;d-cache-size = <32768>;d-tlb-sets = <1>;d-tlb-size = <40>;device_type = "cpu";i-cache-block-size = <64>;i-cache-sets = <128>;i-cache-size = <32768>;i-tlb-sets = <1>;i-tlb-size = <40>;mmu-type = "riscv,sv39";next-level-cache = <&ccache>;reg = <0x2>;riscv,isa = "rv64imafdc";tlb-split;cpu2_intc: interrupt-controller {#interrupt-cells = <1>;compatible = "riscv,cpu-intc";interrupt-controller;};};cpu3: cpu@3 {compatible = "sifive,bullet0", "riscv";d-cache-block-size = <64>;d-cache-sets = <64>;d-cache-size = <32768>;d-tlb-sets = <1>;d-tlb-size = <40>;device_type = "cpu";i-cache-block-size = <64>;i-cache-sets = <128>;i-cache-size = <32768>;i-tlb-sets = <1>;i-tlb-size = <40>;mmu-type = "riscv,sv39";next-level-cache = <&ccache>;reg = <0x3>;riscv,isa = "rv64imafdc";tlb-split;cpu3_intc: interrupt-controller {#interrupt-cells = <1>;compatible = "riscv,cpu-intc";interrupt-controller;};};cpu4: cpu@4 {compatible = "sifive,bullet0", "riscv";d-cache-block-size = <64>;d-cache-sets = <64>;d-cache-size = <32768>;d-tlb-sets = <1>;d-tlb-size = <40>;device_type = "cpu";i-cache-block-size = <64>;i-cache-sets = <128>;i-cache-size = <32768>;i-tlb-sets = <1>;i-tlb-size = <40>;mmu-type = "riscv,sv39";next-level-cache = <&ccache>;reg = <0x4>;riscv,isa = "rv64imafdc";tlb-split;cpu4_intc: interrupt-controller {#interrupt-cells = <1>;compatible = "riscv,cpu-intc";interrupt-controller;};};};soc {#address-cells = <2>;#size-cells = <2>;compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus";ranges;plic0: interrupt-controller@c000000 {#interrupt-cells = <1>;compatible = "sifive,plic-1.0.0";reg = <0x0 0xc000000 0x0 0x4000000>;riscv,ndev = <69>;interrupt-controller;interrupts-extended = <&cpu0_intc 0xffffffff&cpu1_intc 0xffffffff &cpu1_intc 9&cpu2_intc 0xffffffff &cpu2_intc 9&cpu3_intc 0xffffffff &cpu3_intc 9&cpu4_intc 0xffffffff &cpu4_intc 9>;};prci: clock-controller@10000000 {compatible = "sifive,fu740-c000-prci";reg = <0x0 0x10000000 0x0 0x1000>;clocks = <&hfclk>, <&rtcclk>;#clock-cells = <1>;#reset-cells = <1>;};uart0: serial@10010000 {compatible = "sifive,fu740-c000-uart", "sifive,uart0";reg = <0x0 0x10010000 0x0 0x1000>;interrupt-parent = <&plic0>;interrupts = <39>;clocks = <&prci PRCI_CLK_PCLK>;status = "disabled";};uart1: serial@10011000 {compatible = "sifive,fu740-c000-uart", "sifive,uart0";reg = <0x0 0x10011000 0x0 0x1000>;interrupt-parent = <&plic0>;interrupts = <40>;clocks = <&prci PRCI_CLK_PCLK>;status = "disabled";};i2c0: i2c@10030000 {compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";reg = <0x0 0x10030000 0x0 0x1000>;interrupt-parent = <&plic0>;interrupts = <52>;clocks = <&prci PRCI_CLK_PCLK>;reg-shift = <2>;reg-io-width = <1>;#address-cells = <1>;#size-cells = <0>;status = "disabled";};i2c1: i2c@10031000 {compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";reg = <0x0 0x10031000 0x0 0x1000>;interrupt-parent = <&plic0>;interrupts = <53>;clocks = <&prci PRCI_CLK_PCLK>;reg-shift = <2>;reg-io-width = <1>;#address-cells = <1>;#size-cells = <0>;status = "disabled";};qspi0: spi@10040000 {compatible = "sifive,fu740-c000-spi", "sifive,spi0";reg = <0x0 0x10040000 0x0 0x10000x0 0x20000000 0x0 0x10000000>;interrupt-parent = <&plic0>;interrupts = <41>;clocks = <&prci PRCI_CLK_PCLK>;#address-cells = <1>;#size-cells = <0>;status = "disabled";};qspi1: spi@10041000 {compatible = "sifive,fu740-c000-spi", "sifive,spi0";reg = <0x0 0x10041000 0x0 0x10000x0 0x30000000 0x0 0x10000000>;interrupt-parent = <&plic0>;interrupts = <42>;clocks = <&prci PRCI_CLK_PCLK>;#address-cells = <1>;#size-cells = <0>;status = "disabled";};spi0: spi@10050000 {compatible = "sifive,fu740-c000-spi", "sifive,spi0";reg = <0x0 0x10050000 0x0 0x1000>;interrupt-parent = <&plic0>;interrupts = <43>;clocks = <&prci PRCI_CLK_PCLK>;#address-cells = <1>;#size-cells = <0>;status = "disabled";};eth0: ethernet@10090000 {compatible = "sifive,fu740-c000-gem";interrupt-parent = <&plic0>;interrupts = <55>;reg = <0x0 0x10090000 0x0 0x20000x0 0x100a0000 0x0 0x1000>;local-mac-address = [00 00 00 00 00 00];clock-names = "pclk", "hclk";clocks = <&prci PRCI_CLK_GEMGXLPLL>,<&prci PRCI_CLK_GEMGXLPLL>;#address-cells = <1>;#size-cells = <0>;status = "disabled";};pwm0: pwm@10020000 {compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";reg = <0x0 0x10020000 0x0 0x1000>;interrupt-parent = <&plic0>;interrupts = <44 45 46 47>;clocks = <&prci PRCI_CLK_PCLK>;#pwm-cells = <3>;status = "disabled";};pwm1: pwm@10021000 {compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";reg = <0x0 0x10021000 0x0 0x1000>;interrupt-parent = <&plic0>;interrupts = <48 49 50 51>;clocks = <&prci PRCI_CLK_PCLK>;#pwm-cells = <3>;status = "disabled";};ccache: cache-controller@2010000 {compatible = "sifive,fu740-c000-ccache", "cache";cache-block-size = <64>;cache-level = <2>;cache-sets = <2048>;cache-size = <2097152>;cache-unified;interrupt-parent = <&plic0>;interrupts = <19 21 22 20>;reg = <0x0 0x2010000 0x0 0x1000>;};gpio: gpio@10060000 {compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";interrupt-parent = <&plic0>;interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,<30>, <31>, <32>, <33>, <34>, <35>, <36>,<37>, <38>;reg = <0x0 0x10060000 0x0 0x1000>;gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;clocks = <&prci PRCI_CLK_PCLK>;status = "disabled";};pcie@e00000000 {#address-cells = <3>;#interrupt-cells = <1>;#num-lanes = <8>;#size-cells = <2>;compatible = "sifive,fu740-pcie";reg = <0xe 0x00000000 0x1 0x00xd 0xf0000000 0x0 0x100000000x0 0x100d0000 0x0 0x1000>;reg-names = "dbi", "config", "mgmt";device_type = "pci";dma-coherent;bus-range = <0x0 0xff>;ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x100000x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff700000x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x10000000xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;num-lanes = <0x8>;interrupts = <56 57 58 59 60 61 62 63 64>;interrupt-names = "msi", "inta", "intb", "intc", "intd";interrupt-parent = <&plic0>;interrupt-map-mask = <0x0 0x0 0x0 0x7>;interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,<0x0 0x0 0x0 0x2 &plic0 58>,<0x0 0x0 0x0 0x3 &plic0 59>,<0x0 0x0 0x0 0x4 &plic0 60>;pwren-gpios = <&gpio 5 0>;perstn-gpios = <&gpio 8 0>;clocks = <&prci PRCI_CLK_PCIEAUX>;clock-names = "pcieaux";resets = <&prci PRCI_RST_PCIE_POWER_UP_N>;reset-names = "rst_n";status = "okay";};};+}; diff --git a/include/dt-bindings/clock/sifive-fu740-prci.h b/include/dt-bindings/clock/sifive-fu740-prci.h new file mode 100644 index 0000000..8bf78c2 --- /dev/null +++ b/include/dt-bindings/clock/sifive-fu740-prci.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */
Can you please make this (GPL-2.0 OR MIT)?
+/*
- Copyright (C) 2020-2021 SiFive, Inc.
- Wesley Terpstra
- Paul Walmsley
- Zong Li
- Pragnesh Patel
- */
+#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H +#define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
+/* Clock indexes for use by Device Tree data and the PRCI driver */
+#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_DVFSCOREPLL 3 +#define PRCI_CLK_HFPCLKPLL 4 +#define PRCI_CLK_CLTXPLL 5 +#define PRCI_CLK_TLCLK 6 +#define PRCI_CLK_PCLK 7 +#define PRCI_CLK_PCIEAUX 8
+#endif diff --git a/include/dt-bindings/reset/sifive-fu740-prci.h b/include/dt-bindings/reset/sifive-fu740-prci.h new file mode 100644 index 0000000..cff6e02 --- /dev/null +++ b/include/dt-bindings/reset/sifive-fu740-prci.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */
Ditto
+/*
- Copyright (C) 2020-2021 Sifive, Inc.
- Author: Pragnesh Patel pragnesh.patel@sifive.com
- */
+#ifndef __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H +#define __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H
+/* Reset indexes for use by device tree data and the PRCI driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +#define PRCI_RST_PCIE_POWER_UP_N 4 +#define PRCI_RST_GEMGXL_N 5 +#define PRCI_RST_CLTX_N 6
+#endif
Otherwise LGTM Reviewed-by: Bin Meng bmeng.cn@gmail.com