Enable ACPI table generation by creating a DSDT table for all baytrail boards: conga-qeval20-qa3-e3845, bayleybay and minnowmax.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Stefan Roese sr@denx.de Tested-by: Stefan Roese sr@denx.de ---
Changes in v2: None
board/congatec/conga-qeval20-qa3-e3845/Makefile | 1 + board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl | 13 +++++++++++++ board/congatec/conga-qeval20-qa3-e3845/dsdt.asl | 14 ++++++++++++++ board/intel/bayleybay/Makefile | 1 + board/intel/bayleybay/acpi/mainboard.asl | 11 +++++++++++ board/intel/bayleybay/dsdt.asl | 14 ++++++++++++++ board/intel/minnowmax/Makefile | 1 + board/intel/minnowmax/acpi/mainboard.asl | 11 +++++++++++ board/intel/minnowmax/dsdt.asl | 14 ++++++++++++++ configs/bayleybay_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/minnowmax_defconfig | 1 + 12 files changed, 83 insertions(+) create mode 100644 board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl create mode 100644 board/congatec/conga-qeval20-qa3-e3845/dsdt.asl create mode 100644 board/intel/bayleybay/acpi/mainboard.asl create mode 100644 board/intel/bayleybay/dsdt.asl create mode 100644 board/intel/minnowmax/acpi/mainboard.asl create mode 100644 board/intel/minnowmax/dsdt.asl
diff --git a/board/congatec/conga-qeval20-qa3-e3845/Makefile b/board/congatec/conga-qeval20-qa3-e3845/Makefile index 23b8748..b784510 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/Makefile +++ b/board/congatec/conga-qeval20-qa3-e3845/Makefile @@ -5,3 +5,4 @@ #
obj-y += conga-qeval20-qa3.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl b/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl new file mode 100644 index 0000000..eace459 --- /dev/null +++ b/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} + +/* TODO: Need add Winbond SuperIO chipset W83627 ASL codes */ diff --git a/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl b/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl new file mode 100644 index 0000000..6042011 --- /dev/null +++ b/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/board/intel/bayleybay/Makefile b/board/intel/bayleybay/Makefile index 88b5aad..52dda7d 100644 --- a/board/intel/bayleybay/Makefile +++ b/board/intel/bayleybay/Makefile @@ -5,3 +5,4 @@ #
obj-y += bayleybay.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/intel/bayleybay/acpi/mainboard.asl b/board/intel/bayleybay/acpi/mainboard.asl new file mode 100644 index 0000000..21785ea --- /dev/null +++ b/board/intel/bayleybay/acpi/mainboard.asl @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} diff --git a/board/intel/bayleybay/dsdt.asl b/board/intel/bayleybay/dsdt.asl new file mode 100644 index 0000000..6042011 --- /dev/null +++ b/board/intel/bayleybay/dsdt.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile index 1a61432..73e5a8f 100644 --- a/board/intel/minnowmax/Makefile +++ b/board/intel/minnowmax/Makefile @@ -5,3 +5,4 @@ #
obj-y += minnowmax.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/intel/minnowmax/acpi/mainboard.asl b/board/intel/minnowmax/acpi/mainboard.asl new file mode 100644 index 0000000..21785ea --- /dev/null +++ b/board/intel/minnowmax/acpi/mainboard.asl @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} diff --git a/board/intel/minnowmax/dsdt.asl b/board/intel/minnowmax/dsdt.asl new file mode 100644 index 0000000..6042011 --- /dev/null +++ b/board/intel/minnowmax/dsdt.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index dfafb0b..465394e 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -9,6 +9,7 @@ CONFIG_HAVE_VGA_BIOS=y CONFIG_VGA_BIOS_ADDR=0xfffa0000 CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_ACPI_TABLE=y CONFIG_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 24a927d..044045d 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -8,6 +8,7 @@ CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_ACPI_TABLE=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index efb9c1e..cebd660 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -8,6 +8,7 @@ CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_ACPI_TABLE=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y