Hi,
-----Original Message----- From: Marek Vasut marex@denx.de Sent: Saturday, September 21, 2024 9:59 PM To: Chee, Tien Fong tien.fong.chee@intel.com; u-boot@lists.denx.de Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Meng, Tingting tingting.meng@intel.com; Yuslaimi, Alif Zakuan alif.zakuan.yuslaimi@intel.com; Hea, Kok Kiang kok.kiang.hea@intel.com; Rao, Mahesh mahesh.rao@intel.com Subject: Re: [PATCH v1 15/20] arm: socfpga: smc: Add memory coherency support to mailbox command
On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
As cache is enabled in U-Boot and disabled in ATF(BL31). We need to perform cache flush of buffers that are shared between U-Boot and ATF using secure monitor calls.
Signed-off-by: Mahesh Rao mahesh.rao@intel.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
arch/arm/mach-socfpga/smc_api.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c index ebaa0b8fa17..dac888c399f 100644 --- a/arch/arm/mach-socfpga/smc_api.c +++ b/arch/arm/mach-socfpga/smc_api.c @@ -1,9 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ /*
- Copyright (C) 2020 Intel Corporation <www.intel.com>
*/
- Copyright (C) 2020-2024 Intel Corporation <www.intel.com>
+#include <cpu_func.h> #include <asm/ptrace.h> #include <asm/system.h> #include <linux/errno.h> @@ -40,10 +41,16 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg,
u8 urgent, u32 *resp_buf_len,
args[2] = len; args[3] = urgent; args[4] = (u64)resp_buf;
- if (resp_buf_len)
- if (arg && len > 0)
flush_dcache_range((u64)arg, (u64)arg + len);If really needed, the cast should be some uintptr_t
Sure, we will fix it.
Regards, Tien Fong