Even for the single core cortex-a7, SMP bit should be set before enabling MMU and cache.
Reference: Cortex A7 r0p5 TRM. section 4.3.31.
On Fri, Jan 13, 2017 at 12:41 PM, Icenowy Zheng icenowy@aosc.xyz wrote:
13.01.2017, 09:34, "Andre Przywara" andre.przywara@arm.com:
Instead of enumerating all SoC families that need that bit set, let's just express this more clearly: The SMP bits needs to be set on SMP capable ARMv7 CPUs. It's much easier to Kconfig to express it the other way round, so we use ! NO_SMP and ! ARM64.
How about single-core Cortex-A7?
Signed-off-by: Andre Przywara andre.przywara@arm.com
arch/arm/mach-sunxi/board.c | 5 +---- board/sunxi/Kconfig | 6 ++++++ 2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 58fbacb..5a63124 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -180,10 +180,7 @@ void s_init(void) /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */ #endif
-#if defined CONFIG_MACH_SUN6I || \
- defined CONFIG_MACH_SUN7I || \
- defined CONFIG_MACH_SUN8I || \
- defined CONFIG_MACH_SUN9I
+#if !defined(CONFIG_SUNXI_NO_SMP) && !defined(CONFIG_ARM64) /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ asm volatile( "mrc p15, 0, r0, c1, c0, 1\n" diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 37b4252..79b6fa7 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -27,6 +27,10 @@ config SPL_POWER_SUPPORT config SPL_SERIAL_SUPPORT default y
+config SUNXI_NO_SMP
- bool
- default n
# Note only one of these may be selected at a time! But hidden choices are # not supported by Kconfig config SUNXI_GEN_SUN4I @@ -50,12 +54,14 @@ choice config MACH_SUN4I bool "sun4i (Allwinner A10)" select CPU_V7
- select SUNXI_NO_SMP select SUNXI_GEN_SUN4I select SUPPORT_SPL
config MACH_SUN5I bool "sun5i (Allwinner A13)" select CPU_V7
- select SUNXI_NO_SMP select SUNXI_GEN_SUN4I select SUPPORT_SPL
-- 2.8.2
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