Here are my UPM settings and the initdram function. My chip is is MT48LC8M16A2, and there are two chips wired for 32 bit access on CS#1, 8Mx16 each.
#define _NOT_USED_ 0xFFFFFC25
const uint sdram_table[] = { /* * Single Read. (Offset 00h in UPMA RAM) */ 0x0F07FC04, 0x0FFFFC04, 0X00BDFC04, 0X0FF77C00, 0x1FFFFC05, 0X1FF77C35, 0XEFCABC34, 0X1F357C35,
/* * Burst Read. (Offset 08h in UPMA RAM) */ 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x00FFFC00, 0x00FFFC00, 0X00FFFC00, 0X0FF77C00, 0X1FFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, 0X0FF5F005, 0X1FFFFC05,
/* * Single Write. (Offset 18h in UPMA RAM) */ 0x0F07FC04, 0X0FFFFC00, 0X00BD7C04, 0x0FFFFC04, 0x0FF77C04, 0X1FFFFC05, _NOT_USED_, _NOT_USED_,
/* * Burst Write. (Offset 20h in UPMA RAM) */ 0x0F07FC04, 0x0FFFFC00, 0x00BD7C00, 0x00FFFC00, 0x00FFFC00, 0x00FFFC04, 0X0FFFFC04, 0X0FF77C04, 0X1FFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* * Refresh. (Offset 30h in UPMA RAM) */ 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04, 0X0FFFFC84, 0X1FFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* * Exception. (Offset 3Ch in UPMA RAM) */ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size10;
memctl->memc_mdr = 0; memctl->memc_mcr = 0x3f; upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint));
/* Refresh clock prescalar */ memctl->memc_mptpr = MPTPR_PTP_DIV16;
/* Map controller banks 1 to the SDRAM bank */ memctl->memc_or1 = CFG_OR1_PRELIM; memctl->memc_br1 = CFG_BR1_PRELIM;
memctl->memc_mamr = MAMR_32M & (~(MAMR_PTAE));(0x2e902114) /* no refresh yet */
memctl->memc_mbmr = 0; udelay (200);
/* perform SDRAM initializsation sequence */
memctl->memc_mar = 0x00000088; memctl->memc_mcr = 0x80002105; memctl->memc_mcr = 0x80002830; memctl->memc_mcr = 0x80002106;
udelay (1000);
size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
memctl->memc_mamr |= MAMR_PTAE; return (size10); }
I do not have the upm config tool from motorola to verify these settings. Has anybody used this chip with mpc855T and can help me figure this out?
Thanks in advance.
Lokesh
-----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Friday, June 25, 2004 3:26 PM To: Lokesh Kumar Cc: u-boot-users@lists.sourceforge.net Subject: Re: [U-Boot-Users] u-boot and 2.4.18 kernel problem
In message 294FD9D3403A0340BDAC38E48DCEFFDC9355A2@RES-EXCH you wrote:
My board runs at 49.152 MHz and has 16MB flash and 32 MB SDRAM. I have checked my SDRAM UPMA settings and cannot find anything wrong with it.
Then check the rest of the SDRAM initialization sequence, which is much more important that the UPM settings. Yes, this is a FAQ.
Best regards,
Wolfgang Denk