This bus controller is used to communicate with an X-Powers AXP PMIC. Currently, various drivers access PMIC registers through a platform- specific non-DM "pmic_bus" interface, which depends on the legacy I2C framework. In order to convert those drivers to use DM_PMIC, this bus needs a DM_I2C driver.
Since the non-DM bus controller driver is still needed in SPL, the quick solution is to implement the DM_I2C ops using the existing functions.
The register for switching between I2C/P2WI/RSB mode is the same across all PMIC variants, so move that to the common header.
There are only a couple of pairs of hardware/runtime addresses used across all PMIC variants. So far the code expected only the "primary" pair, but some PMICs like the AXP305 and AXP805 use the secondary pair, so add support for that to the DM driver as well.
Signed-off-by: Samuel Holland samuel@sholland.org ---
arch/arm/mach-sunxi/Kconfig | 8 ---- arch/arm/mach-sunxi/pmic_bus.c | 11 ++--- drivers/i2c/Kconfig | 8 ++++ drivers/i2c/Makefile | 1 + drivers/i2c/sun8i_rsb.c | 86 ++++++++++++++++++++++++++++++++++ include/axp_pmic.h | 6 +++ 6 files changed, 105 insertions(+), 15 deletions(-) create mode 100644 drivers/i2c/sun8i_rsb.c
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 37076c2dfb3..3a1916759dc 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -100,14 +100,6 @@ config AXP_PMIC_BUS Select this PMIC bus access helpers for Sunxi platform PRCM or other AXP family PMIC devices.
-config SUN8I_RSB - bool "Allwinner sunXi Reduced Serial Bus Driver" - help - Say y here to enable support for Allwinner's Reduced Serial Bus - (RSB) support. This controller is responsible for communicating - with various RSB based devices, such as AXP223, AXP8XX PMICs, - and AC100/AC200 ICs. - config SUNXI_SRAM_ADDRESS hex default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5 diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c index 673a05fdd16..827797249ea 100644 --- a/arch/arm/mach-sunxi/pmic_bus.c +++ b/arch/arm/mach-sunxi/pmic_bus.c @@ -23,10 +23,6 @@
#define AXP221_CHIP_ADDR 0x68
-/* AXP818 device and runtime addresses are same as AXP223 */ -#define AXP223_DEVICE_ADDR 0x3a3 -#define AXP223_RUNTIME_ADDR 0x2d - int pmic_bus_init(void) { /* This cannot be 0 because it is used in SPL before BSS is ready */ @@ -49,7 +45,8 @@ int pmic_bus_init(void) if (ret) return ret;
- ret = rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR); + ret = rsb_set_device_address(AXP_PMIC_PRI_DEVICE_ADDR, + AXP_PMIC_PRI_RUNTIME_ADDR); # endif if (ret) return ret; @@ -73,7 +70,7 @@ int pmic_bus_read(u8 reg, u8 *data) # elif defined CONFIG_MACH_SUN8I_R40 return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); # else - return rsb_read(AXP223_RUNTIME_ADDR, reg, data); + return rsb_read(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data); # endif #endif } @@ -92,7 +89,7 @@ int pmic_bus_write(u8 reg, u8 data) # elif defined CONFIG_MACH_SUN8I_R40 return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); # else - return rsb_write(AXP223_RUNTIME_ADDR, reg, data); + return rsb_write(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data); # endif #endif } diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index d082676c4b2..3d97be7a1de 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -585,6 +585,14 @@ config SUN6I_P2WI in the Allwinner A31 and A31s SOCs. This interface is used to connect to specific devices like the X-Powers AXP221 PMIC.
+config SUN8I_RSB + bool "Allwinner sun8i Reduced Serial Bus controller" + depends on ARCH_SUNXI + help + Support for Allwinner's Reduced Serial Bus (RSB) controller. This + controller is responsible for communicating with various RSB based + devices, such as X-Powers AXPxxx PMICs and AC100/AC200 CODEC ICs. + config SYS_I2C_SYNQUACER bool "Socionext SynQuacer I2C controller" depends on ARCH_SYNQUACER && DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 2461f0a2db8..c9e910c4724 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o obj-$(CONFIG_SUN6I_P2WI) += sun6i_p2wi.o +obj-$(CONFIG_SUN8I_RSB) += sun8i_rsb.o obj-$(CONFIG_SYS_I2C_SYNQUACER) += synquacer_i2c.o obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c new file mode 100644 index 00000000000..46d11afa174 --- /dev/null +++ b/drivers/i2c/sun8i_rsb.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <axp_pmic.h> +#include <dm.h> +#include <i2c.h> +#include <asm/arch/rsb.h> + +#if CONFIG_IS_ENABLED(DM_I2C) + +/* + * The mapping from hardware address to runtime address is fixed, and shared + * among all RSB drivers. See the comment in drivers/bus/sunxi-rsb.c in Linux. + */ +static int sun8i_rsb_get_runtime_address(u16 device_addr) +{ + if (device_addr == AXP_PMIC_PRI_DEVICE_ADDR) + return AXP_PMIC_PRI_RUNTIME_ADDR; + if (device_addr == AXP_PMIC_SEC_DEVICE_ADDR) + return AXP_PMIC_SEC_RUNTIME_ADDR; + + return -ENOTSUPP; +} + +static int sun8i_rsb_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + int rtaddr = sun8i_rsb_get_runtime_address(msg->addr); + + if (rtaddr < 0) + return rtaddr; + + /* The hardware only supports SMBus-style transfers. */ + if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1) + return rsb_read(rtaddr, msg[0].buf[0], msg[1].buf); + + if (nmsgs == 1 && msg[0].len == 2) + return rsb_write(rtaddr, msg[0].buf[0], msg[0].buf[1]); + + return -EINVAL; +} + +static int sun8i_rsb_probe_chip(struct udevice *bus, uint chip_addr, + uint chip_flags) +{ + int rtaddr = sun8i_rsb_get_runtime_address(chip_addr); + + if (rtaddr < 0) + return rtaddr; + + return rsb_set_device_address(chip_addr, rtaddr); +} + +static int sun8i_rsb_probe(struct udevice *bus) +{ + return rsb_init(); +} + +static int sun8i_rsb_child_pre_probe(struct udevice *child) +{ + struct dm_i2c_chip *chip = dev_get_parent_plat(child); + + /* Ensure each transfer is for a single register. */ + chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS; + + return 0; +} + +static const struct dm_i2c_ops sun8i_rsb_ops = { + .xfer = sun8i_rsb_xfer, + .probe_chip = sun8i_rsb_probe_chip, +}; + +static const struct udevice_id sun8i_rsb_ids[] = { + { .compatible = "allwinner,sun8i-a23-rsb" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sun8i_rsb) = { + .name = "sun8i_rsb", + .id = UCLASS_I2C, + .of_match = sun8i_rsb_ids, + .probe = sun8i_rsb_probe, + .child_pre_probe = sun8i_rsb_child_pre_probe, + .ops = &sun8i_rsb_ops, +}; + +#endif /* CONFIG_IS_ENABLED(DM_I2C) */ diff --git a/include/axp_pmic.h b/include/axp_pmic.h index 0db3e143eda..46a017d2efa 100644 --- a/include/axp_pmic.h +++ b/include/axp_pmic.h @@ -30,6 +30,12 @@ #define AXP_PMIC_MODE_REG 0x3e #define AXP_PMIC_MODE_I2C 0x00 #define AXP_PMIC_MODE_P2WI 0x3e +#define AXP_PMIC_MODE_RSB 0x7c + +#define AXP_PMIC_PRI_DEVICE_ADDR 0x3a3 +#define AXP_PMIC_PRI_RUNTIME_ADDR 0x2d +#define AXP_PMIC_SEC_DEVICE_ADDR 0x745 +#define AXP_PMIC_SEC_RUNTIME_ADDR 0x3a
int axp_set_dcdc1(unsigned int mvolt); int axp_set_dcdc2(unsigned int mvolt);