Remove the ability for caller code to set MAIR through set_ttbr_tcr_mair() as that doesn't seem to be used nor necessary given that the register is typically initialized once to a compile-time constant, MEMORY_ATTRIBUTES, to be used by the hardware as a byte array to be indexed through the 3-bit attribute entry in PTEs (see MT_NORMAL and MT_DEVICE_*). As those attribute offsets are themselves CPP macros, it is very unlikely for U-Boot to start dynamically defining the value of MAIR at runtime.
For now, keep setting the register from within the function so that no functional change should be expected.
Signed-off-by: Pierre-Clément Tosi ptosi@google.com Cc: Tom Rini trini@konsulko.com Cc: Patrick Delaunay patrick.delaunay@foss.st.com Cc: Patrice Chotard patrice.chotard@foss.st.com --- arch/arm/cpu/armv8/cache_v8.c | 3 +-- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 +++------ arch/arm/include/asm/armv8/mmu.h | 4 +++- 3 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 3de18c7675..b91b61713e 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -415,8 +415,7 @@ __weak void mmu_setup(void) setup_all_pgtables();
el = current_el(); - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), - MEMORY_ATTRIBUTES); + set_ttbr_tcr(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL));
/* enable the mmu */ set_sctlr(get_sctlr() | CR_M); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 2ded3e4efc..5917058fa1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -451,10 +451,8 @@ static inline void early_mmu_setup(void) setup_pgtables();
/* point TTBR to the new table */ - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - get_tcr(el, NULL, NULL) & - ~(TCR_ORGN_MASK | TCR_IRGN_MASK), - MEMORY_ATTRIBUTES); + set_ttbr_tcr(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL) + & ~(TCR_ORGN_MASK | TCR_IRGN_MASK));
set_sctlr(get_sctlr() | CR_M); } @@ -607,8 +605,7 @@ static inline void final_mmu_setup(void) invalidate_icache_all();
/* point TTBR to the new table */ - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), - MEMORY_ATTRIBUTES); + set_ttbr_tcr(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL));
set_sctlr(get_sctlr() | CR_M); } diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 517300e566..7c17c06e98 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -107,8 +107,10 @@
#include <linux/types.h>
-static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) +static inline void set_ttbr_tcr(int el, u64 table, u64 tcr) { + const u64 attr = MEMORY_ATTRIBUTES; + asm volatile("dsb sy"); if (el == 1) { asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");