On 14/06/2012 15:44, Dirk Behme wrote:
From: Michael Langer michael.langer@de.bosch.com
The commit "i.mx: fsl_esdhc: add the i.mx6q support" (4692708d) introduces support for the i.MX6Q MMC host controller USDHC.
MXC_IPG_PERCLK sets the clock to 66MHz. This seems to be the default clock of the ESDHC IP found in < i.MX6 silicon. However, the default clock for the USDHC IP found in i.MX6 is 200MHz (MXC_ESDHC_CLK). This difference will cause a 3 times higher clock on SD_CLK than expected (see fsl_esdh.c -> set_sysctl()).
Signed-off-by: Michael Langer michael.langer@de.bosch.com CC: Stefano Babic sbabic@denx.de CC: Jason Liu r64343@freescale.com
arch/arm/cpu/armv7/imx-common/speed.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/imx-common/speed.c b/arch/arm/cpu/armv7/imx-common/speed.c index 2187e8e..80989c4 100644 --- a/arch/arm/cpu/armv7/imx-common/speed.c +++ b/arch/arm/cpu/armv7/imx-common/speed.c @@ -35,7 +35,11 @@ DECLARE_GLOBAL_DATA_PTR; int get_clocks(void) { #ifdef CONFIG_FSL_ESDHC +#ifdef CONFIG_FSL_USDHC
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#else gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK); #endif +#endif return 0; }
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic