From: Peng Fan peng.fan@nxp.com
This is NXP internal validation board, no longer support it.
Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/Kconfig | 20 - board/freescale/ls1021aqds/Kconfig | 15 - board/freescale/ls1021aqds/MAINTAINERS | 14 - board/freescale/ls1021aqds/Makefile | 9 - board/freescale/ls1021aqds/README | 117 ----- board/freescale/ls1021aqds/ddr.c | 199 -------- board/freescale/ls1021aqds/ddr.h | 61 --- board/freescale/ls1021aqds/ls1021aqds.c | 456 ------------------ board/freescale/ls1021aqds/ls1021aqds_qixis.h | 36 -- board/freescale/ls1021aqds/ls102xa_pbi.cfg | 12 - .../freescale/ls1021aqds/ls102xa_rcw_nand.cfg | 7 - .../ls1021aqds/ls102xa_rcw_sd_ifc.cfg | 14 - .../ls1021aqds/ls102xa_rcw_sd_qspi.cfg | 14 - board/freescale/ls1021aqds/psci.S | 32 -- configs/ls1021aqds_nand_defconfig | 137 ------ configs/ls1021aqds_sdcard_ifc_defconfig | 134 ----- configs/ls1021aqds_sdcard_qspi_defconfig | 123 ----- 17 files changed, 1400 deletions(-) delete mode 100644 board/freescale/ls1021aqds/Kconfig delete mode 100644 board/freescale/ls1021aqds/MAINTAINERS delete mode 100644 board/freescale/ls1021aqds/Makefile delete mode 100644 board/freescale/ls1021aqds/README delete mode 100644 board/freescale/ls1021aqds/ddr.c delete mode 100644 board/freescale/ls1021aqds/ddr.h delete mode 100644 board/freescale/ls1021aqds/ls1021aqds.c delete mode 100644 board/freescale/ls1021aqds/ls1021aqds_qixis.h delete mode 100644 board/freescale/ls1021aqds/ls102xa_pbi.cfg delete mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg delete mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg delete mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg delete mode 100644 board/freescale/ls1021aqds/psci.S delete mode 100644 configs/ls1021aqds_nand_defconfig delete mode 100644 configs/ls1021aqds_sdcard_ifc_defconfig delete mode 100644 configs/ls1021aqds_sdcard_qspi_defconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 752e379e3c1..c004e9256da 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1582,25 +1582,6 @@ config TARGET_LS1088ARDB development platform that supports the QorIQ LS1088A Layerscape Architecture processor.
-config TARGET_LS1021AQDS - bool "Support ls1021aqds" - select ARCH_LS1021A - select ARCH_SUPPORT_PSCI - select BOARD_EARLY_INIT_F - select BOARD_LATE_INIT - select CPU_V7A - select CPU_V7_HAS_NONSEC - select CPU_V7_HAS_VIRT - select LS1_DEEP_SLEEP - select PEN_ADDR_BIG_ENDIAN - select SUPPORT_SPL - select SYS_FSL_DDR - select FSL_DDR_INTERACTIVE - select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI - select GPIO_EXTRA_HEADER - select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI - imply SCSI - config TARGET_LS1021ATWR bool "Support ls1021atwr" select ARCH_LS1021A @@ -2261,7 +2242,6 @@ source "board/freescale/ls2080aqds/Kconfig" source "board/freescale/ls2080ardb/Kconfig" source "board/freescale/ls1088a/Kconfig" source "board/freescale/ls1028a/Kconfig" -source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1043aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/ls1021atsn/Kconfig" diff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig deleted file mode 100644 index 119b9550410..00000000000 --- a/board/freescale/ls1021aqds/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_LS1021AQDS - -config SYS_BOARD - default "ls1021aqds" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "ls102xa" - -config SYS_CONFIG_NAME - default "ls1021aqds" - -endif diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS deleted file mode 100644 index 913d251eeb7..00000000000 --- a/board/freescale/ls1021aqds/MAINTAINERS +++ /dev/null @@ -1,14 +0,0 @@ -LS1021AQDS BOARD -M: Alison Wang alison.wang@nxp.com -S: Maintained -F: board/freescale/ls1021aqds/ -F: include/configs/ls1021aqds.h -F: configs/ls1021aqds_nor_defconfig -F: configs/ls1021aqds_ddr4_nor_defconfig -F: configs/ls1021aqds_ddr4_nor_lpuart_defconfig -F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig -F: configs/ls1021aqds_nor_lpuart_defconfig -F: configs/ls1021aqds_sdcard_ifc_defconfig -F: configs/ls1021aqds_sdcard_qspi_defconfig -F: configs/ls1021aqds_qspi_defconfig -F: configs/ls1021aqds_nand_defconfig diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile deleted file mode 100644 index 8cbf33fa0ce..00000000000 --- a/board/freescale/ls1021aqds/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright 2014 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ls1021aqds.o -obj-y += ddr.o -obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aqds/README b/board/freescale/ls1021aqds/README deleted file mode 100644 index e2ce00165bd..00000000000 --- a/board/freescale/ls1021aqds/README +++ /dev/null @@ -1,117 +0,0 @@ -Overview --------- -The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC. - -LS1021A SoC Overview ------------------- -The QorIQ LS1 family, which includes the LS1021A communications processor, -is built on Layerscape architecture, the industry's first software-aware, -core-agnostic networking architecture to offer unprecedented efficiency -and scale. - -A member of the value-performance tier, the QorIQ LS1021A processor provides -extensive integration and power efficiency for fanless, small form factor -enterprise networking applications. Incorporating dual ARM Cortex-A7 cores -running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark -performance of over 6,000, as well as virtualization support, advanced -security features and the broadest array of high-speed interconnects and -optimized peripheral features ever offered in a sub-3 W processor. - -The QorIQ LS1021A processor features an integrated LCD controller, -CAN controller for implementing industrial protocols, DDR3L/4 running -up to 1600 MHz, integrated security engine and QUICC Engine, and ECC -protection on both L1 and L2 caches. The LS1021A processor is pin- and -software-compatible with the QorIQ LS1020A and LS1022A processors. - -The LS1021A SoC includes the following function and features: - - - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture - - Dual high-preformance ARM Cortex-A7 cores, each core includes: - - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) - - 512 Kbyte shared coherent L2 Cache (with ECC protection) - - NEON Co-processor (per core) - - 40-bit physical addressing - - Vector floating-point support - - ARM Core-Link CCI-400 Cache Coherent Interconnect - - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration - supporting speeds up to 1600Mtps - - ECC and interleaving support - - VeTSEC Ethernet complex - - Up to 3x virtualized 10/100/1000 Ethernet controllers - - MII, RMII, RGMII, and SGMII support - - QoS, lossless flow control, and IEEE 1588 support - - 4-lane 6GHz SerDes - - High speed interconnect (4 SerDes lanes with are muxed for these protocol) - - Two PCI Express Gen2 controllers running at up to 5 GHz - - One Serial ATA 3.0 supporting 6 GT/s operation - - Two SGMII interfaces supporting 1000 Mbps - - Additional peripheral interfaces - - One high-speed USB 3.0 controller with integrated PHY and one high-speed - USB 2.00 controller with ULPI - - Integrated flash controller (IFC) with 16-bit interface - - Quad SPI NOR Flash - - One enhanced Secure digital host controller - - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) - - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power - UARTs - - Three I2C controllers - - Eight FlexTimers four supporting PWM and four FlexCAN ports - - Four GPIO controllers supporting up to 109 general purpose I/O signals - - Integrated advanced audio block: - - Four synchronous audio interfaces (SAI) - - Sony/Philips Digital Interconnect Format (SPDIF) - - Asynchronous Sample Rate Converter (ASRC) - - Hardware based crypto offload engine - - IPSec forwarding at up to 1Gbps - - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported - - Public key hardware accelerator - - True Random Number Generator (NIST Certified) - - Advanced Encryption Standard Accelerators (AESA) - - Data Encryption Standard Accelerators - - QUICC Engine ULite block - - Two universal communication controllers (TDM and HDLC) supporting 64 - multichannels, each running at 64 Kbps - - Support for 256 channels of HDLC - - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported - -LS1021AQDS board Overview -------------------------- - - DDR Controller - - Supports rates of up to 1600 MHz data-rate - - Supports one DDR3LP UDIMM, of single-, dual- types. - - IFC/Local Bus - - NAND flash: 512M 8-bit NAND flash - - NOR: 128MB 16-bit NOR Flash - - Ethernet - - Three on-board RGMII 10/100/1G ethernet ports. - - FPGA - - Clocks - - System and DDR clock (SYSCLK, DDRCLK) - - SERDES clocks - - Power Supplies - - SDHC - - SDHC/SDXC connector - - Other IO - - Two Serial ports - - Three I2C ports - -Memory map ------------ -The addresses in brackets are physical addresses. - -Start Address End Address Description Size -0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB -0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB -0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB -0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB -0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB -0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB -0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB -0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB - -LS1021a rev1.0 Soc specific Options/Settings --------------------------------------------- -If the LS1021a Soc is rev1.0, you need modify the configuration and enable -CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar. diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c deleted file mode 100644 index 4e70acc5a0c..00000000000 --- a/board/freescale/ls1021aqds/ddr.c +++ /dev/null @@ -1,199 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#include <init.h> -#include <log.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <linux/delay.h> -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 3) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - pbsp = udimms[0]; - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->cpo_override = pbsp->cpo_override; - popts->write_data_delay = - pbsp->write_data_delay; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for %lu MT/s\n", - ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); - - /* force DDR bus width to 32 bits */ - popts->data_bus_width = 1; - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 1; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - -#ifdef CONFIG_SYS_FSL_DDR4 - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | - DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ -#else - popts->cswl_override = DDR_CSWL_CS0; - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x58; - - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); -#endif -} - -#ifdef CONFIG_SYS_DDR_RAW_TIMING -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 1073741824u, - .capacity = 1073741824u, - .primary_sdram_width = 32, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1071, - .caslat_x = 0xfe << 4, /* 5,6,7,8 */ - .taa_ps = 13125, - .twr_ps = 15000, - .trcd_ps = 13125, - .trrd_ps = 7500, - .trp_ps = 13125, - .tras_ps = 37500, - .trc_ps = 50625, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 37500, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - static const char dimm_model[] = "Fixed DDR on board"; - - if (((controller_number == 0) && (dimm_number == 0)) || - ((controller_number == 1) && (dimm_number == 0))) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} -#endif - -#if defined(CONFIG_DEEP_SLEEP) -void board_mem_sleep_setup(void) -{ - void __iomem *qixis_base = (void *)QIXIS_BASE; - - /* does not provide HW signals for power management */ - clrbits_8(qixis_base + 0x21, 0x2); - udelay(1); -} -#endif - -int fsl_initdram(void) -{ - phys_size_t dram_size; - -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) - puts("Initializing DDR....using SPD\n"); - dram_size = fsl_ddr_sdram(); -#else - dram_size = fsl_ddr_sdram_size(); -#endif - -#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) - fsl_dp_resume(); -#endif - - erratum_a008850_post(); - - gd->ram_size = dram_size; - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; - - return 0; -} diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h deleted file mode 100644 index 58a88384367..00000000000 --- a/board/freescale/ls1021aqds/ddr.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ - -void erratum_a008850_post(void); - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; - u32 cpo_override; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ -#ifdef CONFIG_SYS_FSL_DDR4 - {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 8, 8, 0x090A0B0B, 0x0C0D0E0C,}, - {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, - {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,}, -#elif defined(CONFIG_SYS_FSL_DDR3) - {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, - {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, -#else -#error DDR type not defined -#endif - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -#endif diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c deleted file mode 100644 index d5cb7312095..00000000000 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ /dev/null @@ -1,456 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019, 2021 NXP - */ - -#include <common.h> -#include <clock_legacy.h> -#include <fdt_support.h> -#include <i2c.h> -#include <init.h> -#include <log.h> -#include <asm/io.h> -#include <asm/arch/immap_ls102xa.h> -#include <asm/arch/clock.h> -#include <asm/arch/fsl_serdes.h> -#include <asm/arch/ls102xa_soc.h> -#include <asm/arch/ls102xa_devdis.h> -#include <hwconfig.h> -#include <mmc.h> -#include <fsl_csu.h> -#include <fsl_ifc.h> -#include <spl.h> -#include <fsl_devdis.h> -#include <fsl_validate.h> -#include <fsl_ddr.h> -#include "../common/i2c_mux.h" -#include "../common/sleep.h" -#include "../common/qixis.h" -#include "ls1021aqds_qixis.h" -#ifdef CONFIG_U_QE -#include <fsl_qe.h> -#endif - -#define PIN_MUX_SEL_CAN 0x03 -#define PIN_MUX_SEL_IIC2 0xa0 -#define PIN_MUX_SEL_RGMII 0x00 -#define PIN_MUX_SEL_SAI 0x0c -#define PIN_MUX_SEL_SDHC 0x00 - -#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value) -#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value) -enum { - MUX_TYPE_CAN, - MUX_TYPE_IIC2, - MUX_TYPE_RGMII, - MUX_TYPE_SAI, - MUX_TYPE_SDHC, - MUX_TYPE_SD_PCI4, - MUX_TYPE_SD_PC_SA_SG_SG, - MUX_TYPE_SD_PC_SA_PC_SG, - MUX_TYPE_SD_PC_SG_SG, -}; - -enum { - GE0_CLK125, - GE2_CLK125, - GE1_CLK125, -}; - -int checkboard(void) -{ -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) - char buf[64]; -#endif -#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) - u8 sw; -#endif - - puts("Board: LS1021AQDS\n"); - -#ifdef CONFIG_SD_BOOT - puts("SD\n"); -#elif CONFIG_QSPI_BOOT - puts("QSPI\n"); -#else - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("PromJet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else if (sw == 0x15) - printf("IFCCard\n"); - else - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); -#endif - -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) - printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", - QIXIS_READ(id), QIXIS_READ(arch)); - - printf("FPGA: v%d (%s), build %d\n", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); -#endif - - return 0; -} - -#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch (sysclk_conf & 0x0f) { - case QIXIS_SYSCLK_64: - return 64000000; - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - return 66666666; -} -#endif - -#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - return 66666666; -} -#endif - -int dram_init(void) -{ - /* - * When resuming from deep sleep, the I2C channel may not be - * in the default channel. So, switch to the default channel - * before accessing DDR SPD. - * - * PCA9547(0x77) mount on I2C1 bus - */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - return fsl_initdram(); -} - -int board_early_init_f(void) -{ - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; - -#ifdef CONFIG_TSEC_ENET - /* clear BD & FR bits for BE BD's and frame data */ - clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); -#endif - -#ifdef CONFIG_FSL_IFC - init_early_memctl_regs(); -#endif - - arch_soc_init(); - -#if defined(CONFIG_DEEP_SLEEP) - if (is_warm_boot()) - fsl_dp_disable_console(); -#endif - - return 0; -} - -#ifdef CONFIG_SPL_BUILD -void board_init_f(ulong dummy) -{ -#ifdef CONFIG_NAND_BOOT - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - u32 porsr1, pinctl; - - /* - * There is LS1 SoC issue where NOR, FPGA are inaccessible during - * NAND boot because IFC signals > IFC_AD7 are not enabled. - * This workaround changes RCW source to make all signals enabled. - */ - porsr1 = in_be32(&gur->porsr1); - pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | - DCFG_CCSR_PORSR1_RCW_SRC_I2C); - out_be32((unsigned int *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), - pinctl); -#endif - - /* Clear the BSS */ - memset(__bss_start, 0, __bss_end - __bss_start); - -#ifdef CONFIG_FSL_IFC - init_early_memctl_regs(); -#endif - - get_clocks(); - -#if defined(CONFIG_DEEP_SLEEP) - if (is_warm_boot()) - fsl_dp_disable_console(); -#endif - - preloader_console_init(); - -#ifdef CONFIG_SPL_I2C - i2c_init_all(); -#endif - - timer_init(); - dram_init(); - - /* Allow OCRAM access permission as R/W */ -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - - board_init_r(NULL, 0); -} -#endif - -void config_etseccm_source(int etsec_gtx_125_mux) -{ - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; - - switch (etsec_gtx_125_mux) { - case GE0_CLK125: - out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125); - debug("etseccm set to GE0_CLK125\n"); - break; - - case GE2_CLK125: - out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); - debug("etseccm set to GE2_CLK125\n"); - break; - - case GE1_CLK125: - out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125); - debug("etseccm set to GE1_CLK125\n"); - break; - - default: - printf("Error! trying to set etseccm to invalid value\n"); - break; - } -} - -int config_board_mux(int ctrl_type) -{ - u8 reg12, reg14; - - reg12 = QIXIS_READ(brdcfg[12]); - reg14 = QIXIS_READ(brdcfg[14]); - - switch (ctrl_type) { - case MUX_TYPE_CAN: - config_etseccm_source(GE2_CLK125); - reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); - break; - case MUX_TYPE_IIC2: - reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); - break; - case MUX_TYPE_RGMII: - reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); - break; - case MUX_TYPE_SAI: - config_etseccm_source(GE2_CLK125); - reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); - break; - case MUX_TYPE_SDHC: - reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); - break; - case MUX_TYPE_SD_PCI4: - reg12 = 0x38; - break; - case MUX_TYPE_SD_PC_SA_SG_SG: - reg12 = 0x01; - break; - case MUX_TYPE_SD_PC_SA_PC_SG: - reg12 = 0x01; - break; - case MUX_TYPE_SD_PC_SG_SG: - reg12 = 0x21; - break; - default: - printf("Wrong mux interface type\n"); - return -1; - } - - QIXIS_WRITE(brdcfg[12], reg12); - QIXIS_WRITE(brdcfg[14], reg14); - - return 0; -} - -int config_serdes_mux(void) -{ - struct ccsr_gur *gur = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR; - u32 cfg; - - cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; - cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; - - switch (cfg) { - case 0x0: - config_board_mux(MUX_TYPE_SD_PCI4); - break; - case 0x30: - config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); - break; - case 0x60: - config_board_mux(MUX_TYPE_SD_PC_SG_SG); - break; - case 0x70: - config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); - break; - default: - printf("SRDS1 prtcl:0x%x\n", cfg); - break; - } - - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ -#ifdef CONFIG_CHAIN_OF_TRUST - fsl_setenv_chain_of_trust(); -#endif - - return 0; -} -#endif - -int misc_init_r(void) -{ - int conflict_flag; - - /* some signals can not enable simultaneous*/ - conflict_flag = 0; - if (hwconfig("sdhc")) - conflict_flag++; - if (hwconfig("iic2")) - conflict_flag++; - if (conflict_flag > 1) { - printf("WARNING: pin conflict !\n"); - return 0; - } - - conflict_flag = 0; - if (hwconfig("rgmii")) - conflict_flag++; - if (hwconfig("can")) - conflict_flag++; - if (hwconfig("sai")) - conflict_flag++; - if (conflict_flag > 1) { - printf("WARNING: pin conflict !\n"); - return 0; - } - - if (hwconfig("can")) - config_board_mux(MUX_TYPE_CAN); - else if (hwconfig("rgmii")) - config_board_mux(MUX_TYPE_RGMII); - else if (hwconfig("sai")) - config_board_mux(MUX_TYPE_SAI); - - if (hwconfig("iic2")) - config_board_mux(MUX_TYPE_IIC2); - else if (hwconfig("sdhc")) - config_board_mux(MUX_TYPE_SDHC); - -#ifdef CONFIG_FSL_DEVICE_DISABLE - device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); -#endif - return 0; -} - -int board_init(void) -{ -#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 - erratum_a010315(); -#endif -#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 - erratum_a009942_check_cpo(); -#endif - - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - -#ifndef CONFIG_SYS_FSL_NO_SERDES - fsl_serdes_init(); - config_serdes_mux(); -#endif - - ls102xa_smmu_stream_id_init(); - -#ifdef CONFIG_U_QE - u_qe_init(); -#endif - - return 0; -} - -#if defined(CONFIG_DEEP_SLEEP) -void board_sleep_prepare(void) -{ -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif -} -#endif - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - - return 0; -} - -u8 flash_read8(void *addr) -{ - return __raw_readb(addr + 1); -} - -void flash_write16(u16 val, void *addr) -{ - u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); - - __raw_writew(shftval, addr); -} - -u16 flash_read16(void *addr) -{ - u16 val = __raw_readw(addr); - - return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); -} diff --git a/board/freescale/ls1021aqds/ls1021aqds_qixis.h b/board/freescale/ls1021aqds/ls1021aqds_qixis.h deleted file mode 100644 index 7ad08a54ea6..00000000000 --- a/board/freescale/ls1021aqds/ls1021aqds_qixis.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __LS1021AQDS_QIXIS_H__ -#define __LS1021AQDS_QIXIS_H__ - -/* Definitions of QIXIS Registers for LS1021AQDS */ - -/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ -#define BRDCFG4_EMISEL_MASK 0xe0 -#define BRDCFG4_EMISEL_SHIFT 5 - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 -#define QIXIS_SYSCLK_150 0x5 -#define QIXIS_SYSCLK_160 0x6 -#define QIXIS_SYSCLK_166 0x7 -#define QIXIS_SYSCLK_64 0x8 - -/* DDRCLK */ -#define QIXIS_DDRCLK_66 0x0 -#define QIXIS_DDRCLK_100 0x1 -#define QIXIS_DDRCLK_125 0x2 -#define QIXIS_DDRCLK_133 0x3 - -#define QIXIS_SRDS1CLK_100 0x0 - -#define QIXIS_DCU_BRDCFG5 0x55 - -#endif diff --git a/board/freescale/ls1021aqds/ls102xa_pbi.cfg b/board/freescale/ls1021aqds/ls102xa_pbi.cfg deleted file mode 100644 index f1a1b63ab77..00000000000 --- a/board/freescale/ls1021aqds/ls102xa_pbi.cfg +++ /dev/null @@ -1,12 +0,0 @@ -#PBI commands - -09570200 ffffffff -09570158 00000300 -8940007c 21f47300 - -#Configure Scratch register -09ee0200 10000000 -#Configure alternate space -09570158 00001000 -#Flush PBL data -096100c0 000FFFFF diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg deleted file mode 100644 index d76e9132e35..00000000000 --- a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# serdes protocol -0608000c 00000000 00000000 00000000 -60000000 00407900 e0106a00 21046000 -00000000 00000000 00000000 00038000 -00000000 001b7200 00000000 00000000 diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg deleted file mode 100644 index f0cf9c2b38d..00000000000 --- a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg +++ /dev/null @@ -1,14 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 - -#enable IFC, disable QSPI and DSPI -0608000c 00000000 00000000 00000000 -60000000 00407900 60040a00 21046000 -00000000 00000000 00000000 00038000 -00000000 001b7200 00000000 00000000 - -#disable IFC, enable QSPI and DSPI -#0608000c 00000000 00000000 00000000 -#60000000 00407900 60040a00 21046000 -#00000000 00000000 00000000 00038000 -#20024800 001b7200 00000000 00000000 diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg deleted file mode 100644 index 10cc4a9ab0b..00000000000 --- a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg +++ /dev/null @@ -1,14 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 - -#enable IFC, disable QSPI and DSPI -#0608000c 00000000 00000000 00000000 -#60000000 00407900 60040a00 21046000 -#00000000 00000000 00000000 00038000 -#00000000 001b7200 00000000 00000000 - -#disable IFC, enable QSPI and DSPI -0608000c 00000000 00000000 00000000 -60000000 00407900 60040a00 21046000 -00000000 00000000 00000000 00038000 -20024800 001b7200 00000000 00000000 diff --git a/board/freescale/ls1021aqds/psci.S b/board/freescale/ls1021aqds/psci.S deleted file mode 100644 index 0f38c934ddf..00000000000 --- a/board/freescale/ls1021aqds/psci.S +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 NXP Semiconductor. - * Author: Wang Dongsheng dongsheng.wang@freescale.com - */ - -#include <config.h> -#include <linux/linkage.h> - -#include <asm/armv7.h> -#include <asm/psci.h> - - .pushsection ._secure.text, "ax" - - .arch_extension sec - - .align 5 - -.globl psci_system_off -psci_system_off: - @ Get QIXIS base address - movw r1, #(QIXIS_BASE & 0xffff) - movt r1, #(QIXIS_BASE >> 16) - - ldrb r2, [r1, #QIXIS_PWR_CTL] - orr r2, r2, #QIXIS_PWR_CTL_POWEROFF - strb r2, [r1, #QIXIS_PWR_CTL] - -1: wfi - b 1b - - .popsection diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig deleted file mode 100644 index c3c6678bb49..00000000000 --- a/configs/ls1021aqds_nand_defconfig +++ /dev/null @@ -1,137 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SPL_SKIP_LOWLEVEL_INIT=y -CONFIG_COUNTER_FREQUENCY=12500000 -CONFIG_TARGET_LS1021AQDS=y -CONFIG_TEXT_BASE=0x82000000 -CONFIG_SYS_MALLOC_LEN=0x1002000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x140000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" -CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_SYS_LOAD_ADDR=0x82000000 -CONFIG_AHCI=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff -CONFIG_SYS_MONITOR_LEN=524288 -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg" -CONFIG_NAND_BOOT=y -CONFIG_BOOTDELAY=3 -CONFIG_SILENT_CONSOLE=y -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_ARCH_MISC_INIT=y -CONFIG_MISC_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_SPL_MAX_SIZE=0x1a000 -CONFIG_SPL_PAD_TO=0x1c000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SPL_FSL_PBL=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x1001d000 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80200000 -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_WATCHDOG=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_BOOTZ=y -CONFIG_SYS_BOOTM_LEN=0x4000000 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="eTSEC1" -CONFIG_SATA=y -CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y -CONFIG_DYNAMIC_DDR_CLK_FREQ=y -CONFIG_SYS_FSL_DDR3=y -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_DDR_RAW_TIMING=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y -CONFIG_SYS_NAND_U_BOOT_OFFS=0x1c000 -CONFIG_PHY_REALTEK=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig deleted file mode 100644 index 07d52c249d0..00000000000 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ /dev/null @@ -1,134 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SPL_SKIP_LOWLEVEL_INIT=y -CONFIG_COUNTER_FREQUENCY=12500000 -CONFIG_TARGET_LS1021AQDS=y -CONFIG_TEXT_BASE=0x82000000 -CONFIG_SYS_MALLOC_LEN=0x1002000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x300000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" -CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_SYS_LOAD_ADDR=0x82000000 -CONFIG_AHCI=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff -CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg" -CONFIG_SD_BOOT=y -CONFIG_BOOTDELAY=3 -CONFIG_SILENT_CONSOLE=y -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_ARCH_MISC_INIT=y -CONFIG_MISC_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_SPL_MAX_SIZE=0x1a000 -CONFIG_SPL_PAD_TO=0x1c000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SPL_FSL_PBL=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x1001d000 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x820c0000 -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR=y -CONFIG_SPL_WATCHDOG=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_BOOTZ=y -CONFIG_SYS_BOOTM_LEN=0x4000000 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="eTSEC1" -CONFIG_SATA=y -CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y -CONFIG_DYNAMIC_DDR_CLK_FREQ=y -CONFIG_SYS_FSL_DDR3=y -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_DDR_RAW_TIMING=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig deleted file mode 100644 index 6834a696b63..00000000000 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ /dev/null @@ -1,123 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SPL_SKIP_LOWLEVEL_INIT=y -CONFIG_COUNTER_FREQUENCY=12500000 -CONFIG_TARGET_LS1021AQDS=y -CONFIG_TEXT_BASE=0x82000000 -CONFIG_SYS_MALLOC_LEN=0x1002000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x300000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" -CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_SYS_LOAD_ADDR=0x82000000 -CONFIG_AHCI=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff -CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg" -CONFIG_SD_BOOT=y -CONFIG_SD_BOOT_QSPI=y -CONFIG_BOOTDELAY=3 -CONFIG_SILENT_CONSOLE=y -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_ARCH_MISC_INIT=y -CONFIG_MISC_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_SPL_MAX_SIZE=0x1a000 -CONFIG_SPL_PAD_TO=0x1c000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SPL_FSL_PBL=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x1001d000 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x820c0000 -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR=y -CONFIG_SPL_WATCHDOG=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_BOOTZ=y -CONFIG_SYS_BOOTM_LEN=0x4000000 -CONFIG_CMD_GREPENV=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="eTSEC1" -CONFIG_SATA=y -CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y -CONFIG_SYS_FSL_DDR3=y -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_DDR_RAW_TIMING=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_DSPI=y -CONFIG_FSL_QSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y