Hi,
On Thu, Feb 15, 2018 at 06:40:53PM +0100, Giulio Benetti wrote:
Differently from other Lcd signals, HSYNC and VSYNC signals result inverted if their bits are cleared to 0.
Invert their settings of IO_POL register.
Signed-off-by: Giulio Benetti giulio.benetti@micronovasrl.com
drivers/video/sunxi/lcdc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c index 4cb86fb..007057c 100644 --- a/drivers/video/sunxi/lcdc.c +++ b/drivers/video/sunxi/lcdc.c @@ -132,9 +132,9 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc, }
val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(dclk_phase);
- if (mode->flags & DISPLAY_FLAGS_HSYNC_LOW)
- if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH) val |= SUNXI_LCDC_TCON_HSYNC_MASK;
- if (mode->flags & DISPLAY_FLAGS_VSYNC_LOW)
- if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH) val |= SUNXI_LCDC_TCON_VSYNC_MASK;
As we discussed earlier, I'm really not sure this is worth it. This is going to break all the boards out there that store the modeline in the environment. And we should fix all the defconfigs (but that's the easy part).
Anatolij, any suggestion?
Thanks! Maxime