diff --git a/Makefile b/Makefile
index 1a0e6c3..41fbc41 100644
--- a/Makefile
+++ b/Makefile
@@ -117,6 +117,7 @@ endif
 ifeq ($(CPU),bf533)
 OBJS += cpu/$(CPU)/start1.o	cpu/$(CPU)/interrupt.o	cpu/$(CPU)/cache.o
 OBJS += cpu/$(CPU)/cplbhdlr.o	cpu/$(CPU)/cplbmgr.o	cpu/$(CPU)/flush.o
+OBJS += cpu/$(CPU)/init_sdram.o
 endif
 
 LIBS  = lib_generic/libgeneric.a
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index aeb7842..c0d70ea 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -1253,6 +1253,7 @@ print_type (image_header_t *hdr)
 	case IH_CPU_MICROBLAZE:	arch = "Microblaze"; 		break;
 	case IH_CPU_NIOS:	arch = "Nios";			break;
 	case IH_CPU_NIOS2:	arch = "Nios-II";		break;
+	case IH_CPU_BLACKFIN:   arch = "Blackfin";              break;
 	default:		arch = "Unknown Architecture";	break;
 	}
 
diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S
index 8fac402..800a0fa 100644
--- a/cpu/bf533/cache.S
+++ b/cpu/bf533/cache.S
@@ -1,8 +1,33 @@
-
-
+/*
+ * U-boot - cache.S
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
 #define ASSEMBLY
 #include <asm/linkage.h>
-#include <asm/cpu/def_LPBlackfin.h>
+#include <config.h>
+#include <asm/blackfin.h>
 
 .text
 .align 2
diff --git a/cpu/bf533/cplbhdlr.S b/cpu/bf533/cplbhdlr.S
index 61be5bb..4eb367a 100644
--- a/cpu/bf533/cplbhdlr.S
+++ b/cpu/bf533/cplbhdlr.S
@@ -1,13 +1,28 @@
-/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
+/*
+ * U-boot - cplbhdlr.S
  *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.
+ * Copyright (c) 2005 blackfin.uclinux.org
  *
- * Blackfin BF533/2.6 support : LG Soft India
- */
-
-
-/* Include an exception handler to invoke the CPLB manager
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
  */
 
 #include <asm-blackfin/linkage.h>
diff --git a/cpu/bf533/cplbmgr.S b/cpu/bf533/cplbmgr.S
index 7a0b048..4d4a5be 100644
--- a/cpu/bf533/cplbmgr.S
+++ b/cpu/bf533/cplbmgr.S
@@ -1,14 +1,28 @@
-/*This file is subject to the terms and conditions of the GNU General Public
- * License.
+/*
+ * U-boot - cplbmgr.S
  *
- * Blackfin BF533/2.6 support : LG Soft India
- * Modification: Dec 07 2004
- *	1. Correction in icheck_lock.  Valid lock entries were
- *	   geting victimized, for instruction cplb replacement.
- *	2. Setup loop's are modified as now toolchain support's P Indexed
- *	   addressing
- *	   :LG Soft India
+ * Copyright (c) 2005 blackfin.uclinux.org
  *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
  */
 
 /* Usage: int _cplb_mgr(is_data_miss,int enable_cache)
@@ -32,6 +46,7 @@
 #define ASSEMBLY
 
 #include <asm-blackfin/linkage.h>
+#include <config.h>
 #include <asm-blackfin/blackfin.h>
 #include <asm-blackfin/cplbtab.h>
 #include <asm-blackfin/cplb.h>
diff --git a/cpu/bf533/cpu.c b/cpu/bf533/cpu.c
index 78e2b96..182fa4e 100644
--- a/cpu/bf533/cpu.c
+++ b/cpu/bf533/cpu.c
@@ -30,7 +30,6 @@
 #include <command.h>
 #include <asm/entry.h>
 
-#define SSYNC() asm("ssync;")
 #define CACHE_ON 1
 #define CACHE_OFF 0
 
@@ -123,18 +122,20 @@ void icache_enable(void)
 		*I1++ = icplb_table[i][1];
 		}
 	cli();
-	SSYNC();
+	__builtin_bfin_ssync();
+	asm(" .align 8; ");
 	*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
-	SSYNC();
+	__builtin_bfin_ssync();
 	sti();
 }
 
 void icache_disable(void)
 {
 	cli();
-	SSYNC();
+	__builtin_bfin_ssync();
+	asm(" .align 8; ");
 	*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
-	SSYNC();
+	__builtin_bfin_ssync();
 	sti();
 }
 
@@ -154,6 +155,8 @@ void dcache_enable(void)
 	unsigned int *I0,*I1;
 	unsigned int temp;
 	int i;
+	/* Before enable dcache, disable it first */
+	dcache_disable();
 	I0 = (unsigned int *)DCPLB_ADDR0;
 	I1 = (unsigned int *)DCPLB_DATA0;
 
@@ -163,18 +166,22 @@ void dcache_enable(void)
 		}
 	cli();
 	temp = *(unsigned int *)DMEM_CONTROL;
-	SSYNC();
-	*(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE |ENDCPLB |PORT_PREF0|temp;
-	SSYNC();
+	__builtin_bfin_ssync();
+	asm(" .align 8; ");
+	*(unsigned int *)DMEM_CONTROL =
+	    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
+	__builtin_bfin_ssync();
 	sti();
 }
 
 void dcache_disable(void)
 {
 	cli();
-	SSYNC();
-	*(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE |ENDCPLB |PORT_PREF0);
-	SSYNC();
+	__builtin_bfin_ssync();
+	asm(" .align 8; ");
+	*(unsigned int *)DMEM_CONTROL &=
+	    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+	__builtin_bfin_ssync();
 	sti();
 }
 
diff --git a/cpu/bf533/flush.S b/cpu/bf533/flush.S
index 9fbdefc..55b2388 100644
--- a/cpu/bf533/flush.S
+++ b/cpu/bf533/flush.S
@@ -1,15 +1,35 @@
-/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
- * Copyright (C) 2004 LG SOft India. All Rights Reserved.
+/*
+ * U-boot - flush.S
  *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.
+ * Copyright (c) 2005 blackfin.uclinux.org
  *
- * Blackfin BF533/2.6 support : LG Soft India
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
  */
+
 #define ASSEMBLY
 
 #include <asm/linkage.h>
 #include <asm/cplb.h>
+#include <config.h>
 #include <asm/blackfin.h>
 
 .text
diff --git a/cpu/bf533/interrupt.S b/cpu/bf533/interrupt.S
index e780dc6..a112e43 100644
--- a/cpu/bf533/interrupt.S
+++ b/cpu/bf533/interrupt.S
@@ -41,10 +41,11 @@
 
 #define ASSEMBLY
 
+#include <config.h>
+#include <asm/blackfin.h>
 #include <asm/hw_irq.h>
 #include <asm/entry.h>
 #include <asm/blackfin_defs.h>
-#include <asm/cpu/bf533_irq.h>
 
 .global blackfin_irq_panic;
 
@@ -363,7 +364,7 @@ evt_system_call:
 	r0 = [SP++];
 	SAVE_CONTEXT
 	sp += -12;
-	call display_excp;
+	call exception_handle;
 	sp += 12;
 	RESTORE_CONTEXT
 	RTI;
@@ -382,7 +383,7 @@ evt_soft_int1:
 	r0 = [SP++];
 	SAVE_CONTEXT
 	sp += -12;
-	call display_excp;
+	call exception_handle;
 	sp += 12;
 	RESTORE_CONTEXT
 	RTI;
diff --git a/cpu/bf533/interrupts.c b/cpu/bf533/interrupts.c
index df1a25e..2d81782 100644
--- a/cpu/bf533/interrupts.c
+++ b/cpu/bf533/interrupts.c
@@ -37,7 +37,8 @@
 #include <common.h>
 #include <asm/machdep.h>
 #include <asm/irq.h>
-#include <asm/cpu/defBF533.h>
+#include <config.h>
+#include <asm/blackfin.h>
 #include "cpu.h"
 
 static ulong timestamp;
diff --git a/cpu/bf533/ints.c b/cpu/bf533/ints.c
index 859f4b2..e8e3474 100644
--- a/cpu/bf533/ints.c
+++ b/cpu/bf533/ints.c
@@ -101,6 +101,16 @@ void blackfin_init_IRQ(void)
 	asm("csync;");
 }
 
+void exception_handle(void)
+{
+#if defined (CONFIG_PANIC_HANG)
+	display_excp();
+#else
+	udelay (100000);        /* allow messages to go out */
+        do_reset (NULL, 0, 0, NULL);
+#endif
+}
+
 void display_excp(void)
 {
 	printf("Exception!\n");
diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S
index 6d58575..c200e26 100644
--- a/cpu/bf533/start.S
+++ b/cpu/bf533/start.S
@@ -32,31 +32,14 @@
 
 /*
  * Note: A change in this file subsequently requires a change in
- *       board/$(board_name)/config.mk for a valid u-boot.bin
+ *       board/$(board_name)/config.mk for a valid u-boot.bin 
  */
 
 #define ASSEMBLY
 
 #include <linux/config.h>
-#include <asm/blackfin.h>
 #include <config.h>
-#include <asm/mem_init.h>
-
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
-#endif
+#include <asm/blackfin.h>
 
 .global _stext;
 .global __bss_start;
@@ -71,13 +54,16 @@
 .global _initialize;
 .global _exit;
 .global flashdataend;
+.global init_sdram;
+.global icache_enable;
+.global dcache_enable;
 
 .text
 _start:
 start:
 _stext:
 
-	R0 = 0x30;
+	R0 = 0x32;
 	SYSCFG = R0;
 	SSYNC;
 
@@ -99,7 +85,7 @@ _stext:
 	p3 = 0;
 	p4 = 0;
 	p5 = 0;
-
+	
 	i0 = 0; /* DAG Registers zero'd */
 	i1 = 0;
 	i2 = 0;
@@ -120,8 +106,9 @@ _stext:
 	/* Set loop counters to zero, to make sure that
 	 * hw loops are disabled.
 	 */
-	lc0 = 0;
-	lc1 = 0;
+	r0  = 0;
+	lc0 = r0;
+	lc1 = r0;
 
 	SSYNC;
 
@@ -149,106 +136,37 @@ no_soft_reset:
 	r1 = 0;
 	LSETUP(4,4) lc0 = p1;
 	[ p0 ++ ] = r1;
+	
+	p0.h = hi(SIC_IWR);
+        p0.l = lo(SIC_IWR);
+        r0.l = 0x1;
+        w[p0] = r0.l;
+        SSYNC;
 
-	/*
-	 *  Set PLL_CTL
-	 *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
-	 *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
-	 *   - [7]     = output delay (add 200ps of delay to mem signals)
-	 *   - [6]     = input delay (add 200ps of input delay to mem signals)
-	 *   - [5]     = PDWN      : 1=All Clocks off
-	 *   - [3]     = STOPCK    : 1=Core Clock off
-	 *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
-	 *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
-	 *   all other bits set to zero
-	 */
-
-	r0 = CONFIG_VCO_MULT;	/* Load the VCO multiplier */
-	r0 = r0 << 9;		/* Shift it over */
-	r1 =  CONFIG_CLKIN_HALF;	/* Do we need to divide CLKIN by 2? */
-	r0 = r1 | r0;
-	r1 = CONFIG_PLL_BYPASS;	/* Bypass the PLL?                 */
-	r1 = r1 << 8;	/* Shift it over */
-	r0 = r1 | r0;	/* add them all together */
-
-	p0.h = (PLL_CTL >> 16);
-	p0.l = (PLL_CTL & 0xFFFF);	/* Load the address */
-	cli r2;				/* Disable interrupts */
-	w[p0] = r0;			/* Set the value */
-	idle;				/* Wait for the PLL to stablize */
-	sti r2;				/* Enable interrupts */
-	ssync;
-
-	/*
-	 * Turn on the CYCLES COUNTER
-	 */
-	r2 = SYSCFG;
-	BITSET (r2,1);
-	SYSCFG = r2;
-
-	/* Configure SCLK & CCLK Dividers */
-	r0 = CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV;
-	p0.h = (PLL_DIV >> 16);
-	p0.l = (PLL_DIV & 0xFFFF);
-	w[p0] = r0;
-	ssync;
-
-wait_for_pll_stab:
-	p0.h = (PLL_STAT >> 16);
-	p0.l = (PLL_STAT & 0xFFFF);
-	r0.l = w[p0];
-	cc = bittst(r0,5);
-	if !cc jump wait_for_pll_stab;
-
-	/* Configure SDRAM if SDRAM is already not enabled */
-	p0.l = (EBIU_SDSTAT & 0xFFFF);
-	p0.h = (EBIU_SDSTAT >> 16);
-	r0.l = w[p0];
-	cc = bittst(r0, 3);
-	if !cc jump skip_sdram_enable;
-
-	/* SDRAM initialization */
-	p0.l = (EBIU_SDGCTL & 0xFFFF);
-	p0.h = (EBIU_SDGCTL >> 16);	/* SDRAM Memory Global Control Register */
-	r0.h = (mem_SDGCTL >> 16);
-	r0.l = (mem_SDGCTL & 0xFFFF);
-	[p0] = r0;
-	ssync;
-
-	p0.l = (EBIU_SDBCTL & 0xFFFF);
-	p0.h = (EBIU_SDBCTL >> 16);	/* SDRAM Memory Bank Control Register */
-	r0 = mem_SDBCTL;
-	w[p0] = r0.l;
-	ssync;
-
-	p0.l = (EBIU_SDRRC & 0xFFFF);
-	p0.h = (EBIU_SDRRC >> 16);	/* SDRAM Refresh Rate Control Register */
-	r0 = mem_SDRRC;
-	w[p0] = r0.l;
-	ssync;
+	sp.l = (0xffb01000 & 0xFFFF);
+	sp.h = (0xffb01000 >> 16);
 
-skip_sdram_enable:
-	nop;
+	call init_sdram;
 
-#ifndef	CFG_NO_FLASH
 	/* relocate into to RAM */
-	p1.l = (CFG_FLASH_BASE & 0xffff);
-	p1.h = (CFG_FLASH_BASE >> 16);
+	call get_pc;
+offset:
+	r1.l = ((offset -start) & 0xffff);
+	r1.h = ((offset -start) >> 16);
+	r0 = r0 - r1;
+	p1 = r0;
+
 	p2.l = (CFG_MONITOR_BASE & 0xffff);
 	p2.h = (CFG_MONITOR_BASE >> 16);
-	r0.l = (CFG_MONITOR_LEN & 0xffff);
-	r0.h = (CFG_MONITOR_LEN >> 16);
+
+	p3 = 0x04;
+	p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
+	p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
 loop1:
-	r1 = [p1];
-	[p2] = r1;
-	p3=0x4;
-	p1=p1+p3;
-	p2=p2+p3;
-	r2=0x4;
-	r0=r0-r2;
-	cc=r0==0x0;
+	r1 = [p1 ++ p3];
+	[p2 ++ p3] = r1;
+	cc=p2==p4;
 	if !cc jump loop1;
-#endif
 	/*
 	 * configure STACK
 	 */
@@ -273,7 +191,8 @@ loop1:
 
 	p0.l = (IMASK & 0xFFFF);
 	p0.h = (IMASK >> 16);
-	r0 = IVG15_POS;
+	r0.l = LO(IVG15_POS);
+	r0.h = HI(IVG15_POS);
 	[p0] = r0;
 	raise 15;
 	p0.l = WAIT_HERE;
@@ -288,34 +207,6 @@ WAIT_HERE:
 _real_start:
 	[ -- sp ] = reti;
 
-#ifdef CONFIG_EZKIT533
-	p0.l = (WDOG_CTL & 0xFFFF);
-	p0.h = (WDOG_CTL >> 16);
-	r0 = WATCHDOG_DISABLE(z);
-	w[p0] = r0;
-#endif
-
-	/* Code for initializing Async mem banks */
-	p2.h = (EBIU_AMBCTL1 >> 16);
-	p2.l = (EBIU_AMBCTL1 & 0xFFFF);
-	r0.h = (AMBCTL1VAL >> 16);
-	r0.l = (AMBCTL1VAL & 0xFFFF);
-	[p2] = r0;
-	ssync;
-
-	p2.h = (EBIU_AMBCTL0 >> 16);
-	p2.l = (EBIU_AMBCTL0 & 0xFFFF);
-	r0.h = (AMBCTL0VAL >> 16);
-	r0.l = (AMBCTL0VAL & 0xFFFF);
-	[p2] = r0;
-	ssync;
-
-	p2.h = (EBIU_AMGCTL >> 16);
-	p2.l = (EBIU_AMGCTL & 0xffff);
-	r0 = AMGCTLVAL;
-	w[p2] = r0;
-	ssync;
-
 	/* DMA reset code to Hi of L1 SRAM */
 copy:
 	P1.H = hi(SYSMMR_BASE);	/* P1 Points to the beginning of SYSTEM MMR Space */
@@ -347,53 +238,17 @@ DMA:
 	/* Set Destination DMAConfig = DMA Enable,
 	Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
 	W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
-
-	IDLE;	/* Wait for DMA to Complete */
-
-	R0 = 0x1;
-	W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;	/* Write 1 to clear DMA interrupt */
-
-	/* DMA reset code to DATA BANK A which uses this port
-	 * to avoid following problem
-	 * " Data from a Data Cache fill can be corrupoted after or during
-	 *   instruction DMA if certain core stalls exist"
-	 */
-
-copy_as_data:
-	R0.H = reset_start;	/* Source Address (high) */
-	R0.L = reset_start;	/* Source Address (low) */
-	R1.H = reset_end;
-	R1.L = reset_end;
-	R2 = R1 - R0;	/* Count */
-	R1.H = hi(DATA_BANKA_SRAM);	/* Destination Address (high) */
-	R1.L = lo(DATA_BANKA_SRAM);	/* Destination Address (low) */
-	R3.L = DMAEN;	/* Source DMAConfig Value (8-bit words) */
-	R4.L = (DI_EN | WNR | DMAEN);	/* Destination DMAConfig Value (8-bit words) */
-
-DMA_DATA:
-	R6 = 0x1 (Z);
-	W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6;	/* Source Modify = 1 */
-	W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6;	/* Destination Modify = 1 */
-
- 	[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0;	/* Set Source Base Address */
-	W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2;	/* Set Source Count */
-	/* Set Source      DMAConfig = DMA Enable,
-	Memory Read,  8-Bit Transfers, 1-D DMA, Flow - Stop */
-	W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
-
-	[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;	/* Set Destination Base Address */
-	W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2;	/* Set Destination Count */
-	/* Set Destination DMAConfig = DMA Enable,
-	Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
-	W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
-
-	IDLE;	/* Wait for DMA to Complete */
+	
+WAIT_DMA_DONE:	
+	p0.h = hi(MDMA_D0_IRQ_STATUS);
+	p0.l = lo(MDMA_D0_IRQ_STATUS);
+	R0 = W[P0](Z);
+	CC = BITTST(R0, 0);
+	if ! CC jump WAIT_DMA_DONE
 
 	R0 = 0x1;
 	W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;	/* Write 1 to clear DMA interrupt */
 
-copy_end: nop;
-
 	/* Initialize BSS Section with 0 s */
 	p1.l = __bss_start;
 	p1.h = __bss_start;
@@ -413,6 +268,9 @@ _clear_bss_end:
  	[p1++] = r0;
 _clear_bss_skip:
 
+	call icache_enable;
+	call dcache_enable;
+
 	p0.l = _start1;
 	p0.h = _start1;
 	jump (p0);
@@ -433,3 +291,6 @@ reset_end: nop;
 
 _exit:
 	jump.s	_exit;
+get_pc:
+	r0 = rets;
+	rts;
diff --git a/cpu/bf533/start1.S b/cpu/bf533/start1.S
index 6f48124..2d2781f 100644
--- a/cpu/bf533/start1.S
+++ b/cpu/bf533/start1.S
@@ -24,8 +24,8 @@
 
 #define ASSEMBLY
 #include <linux/config.h>
-#include <asm/blackfin.h>
 #include <config.h>
+#include <asm/blackfin.h>
 
 .global	start1;
 .global	_start1;
diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h
index fbdbf30..376363f 100644
--- a/include/asm-blackfin/blackfin.h
+++ b/include/asm-blackfin/blackfin.h
@@ -25,22 +25,16 @@
 #ifndef _BLACKFIN_H_
 #define _BLACKFIN_H_
 
-#include <asm/cpu/defBF533.h>
-#include <asm/cpu/bf533_serial.h>
-
 #ifndef __ASSEMBLY__
 #ifndef ASSEMBLY
 
 #ifdef SHARED_RESOURCES
  #include <asm/shared_resources.h>
 #endif
-#include <asm/cpu/cdefBF53x.h>
 
 #endif
 #endif
 
-#include <asm/cpu/defBF533.h>
-#include <asm/cpu/defBF533_extn.h>
-#include <asm/cpu/bf533_serial.h>
+#include <asm/cpu/cdefBF53x.h>
 
 #endif
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
index 7715f64..bedf59b 100644
--- a/include/asm-blackfin/cplb.h
+++ b/include/asm-blackfin/cplb.h
@@ -1,16 +1,36 @@
-/************************************************************************
+/*
+ * U-boot - ./include/asm/cplb.h
  *
- * cplb.h
+ * Copyright (c) 2005 blackfin.uclinux.org
  *
- * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- ************************************************************************/
-
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
 /* Defines necessary for cplb initialisation routines. */
 
 #ifndef _CPLB_H
 #define _CPLB_H
 
+#define CONFIG_BLKFIN_WT
+
 #define CPLB_ENABLE_ICACHE_P	0
 #define CPLB_ENABLE_DCACHE_P	1
 #define CPLB_ENABLE_DCACHE2_P	2
diff --git a/include/asm-blackfin/cplbtab.h b/include/asm-blackfin/cplbtab.h
index ab7d989..9ad17f5 100644
--- a/include/asm-blackfin/cplbtab.h
+++ b/include/asm-blackfin/cplbtab.h
@@ -1,13 +1,28 @@
-/*This file is subject to the terms and conditions of the GNU General Public
- * License.
+/*
+ * U-boot - ./include/asm/cplbtab.h
  *
- * Blackfin BF533/2.6 support : LG Soft India
- * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
- * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
- *	        shouldn't be victimized. cplbmgr.S search logic is corrected
- *	        to findout the appropriate victim.
- *	     2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
- *	     : LG Soft India
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
  */
 #include <config.h>
 
@@ -39,53 +54,15 @@
 	#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
 	#define SDRAM_DKERNEL 		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
 	#define L1_DMEMORY		(PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
-	#define SDRAM_EBIU		(PAGE_SIZE_1MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+	#define SDRAM_EBIU		(PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
 
 #else  /*Write Through*/
 	#define SDRAM_DGENERIC 		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
 	#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
 	#define SDRAM_DKERNEL 		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
 	#define L1_DMEMORY		(PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
-	#define SDRAM_EBIU		(PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
-#endif
-
-.global icplb_table
-icplb_table:
-.byte4 0xFFA00000;
-.byte4 (L1_IMEMORY);
-.byte4 0x00000000;
-.byte4 (SDRAM_IKERNEL);			/*SDRAM_Page1*/
-.byte4 0x00400000;
-.byte4 (SDRAM_IKERNEL);		/*SDRAM_Page1*/
-.byte4 0x07C00000;
-.byte4 (SDRAM_IKERNEL);		/*SDRAM_Page14*/
-.byte4 0x00800000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page2*/
-.byte4 0x00C00000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page2*/
-.byte4 0x01000000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page4*/
-.byte4 0x01400000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page5*/
-.byte4 0x01800000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page6*/
-.byte4 0x01C00000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page7*/
-#ifndef CONFIG_EZKIT			/*STAMP Memory regions*/
-.byte4 0x02000000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page8*/
-.byte4 0x02400000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page9*/
-.byte4 0x02800000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page10*/
-.byte4 0x02C00000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page11*/
-.byte4 0x03000000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page12*/
-.byte4 0x03400000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page13*/
+	#define SDRAM_EBIU		(PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
 #endif
-.byte4 0xffffffff;			/* end of section - termination*/
 
 .align 4;
 .global ipdt_table
@@ -126,14 +103,8 @@ ipdt_table:
 .byte4  0x03C00000;
 .byte4  (SDRAM_IGENERIC);              /*SDRAM_Page15*/
 #endif
-.byte4  0x20200000;
-.byte4  (SDRAM_EBIU);      /* Async Memory Bank 2 (Secnd)*/
-.byte4  0x20100000;
-.byte4  (SDRAM_EBIU);      /* Async Memory Bank 1 (Prim B)*/
 .byte4  0x20000000;
-.byte4  (SDRAM_EBIU);      /* Async Memory Bank 0 (Prim A)*/
-.byte4  0x20300000;             /*Fix for Network*/
-.byte4  (SDRAM_EBIU);    /*Async Memory bank 3*/
+.byte4  (SDRAM_EBIU);      /* Async Memory Bank */
 
 #ifdef CONFIG_STAMP
 .byte4        0x04000000;
@@ -173,48 +144,6 @@ ipdt_table:
 #endif
 .byte4 0xffffffff;                    /* end of section - termination*/
 
-/*********************************************************************
- *			DCPLB TABLE
- ********************************************************************/
-
-.global dcplb_table
-dcplb_table:
-.byte4	0x00000000;
-.byte4	(SDRAM_DKERNEL);	/*SDRAM_Page1*/
-.byte4	0x00400000;
-.byte4	(SDRAM_DKERNEL);	/*SDRAM_Page1*/
-.byte4	0x07C00000;
-.byte4	(SDRAM_DKERNEL);	/*SDRAM_Page15*/
-.byte4	0x00800000;
-.byte4 	(SDRAM_DGENERIC);	/*SDRAM_Page2*/
-.byte4 	0x00C00000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page3*/
-.byte4	0x01000000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page4*/
-.byte4	0x01400000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page5*/
-.byte4	0x01800000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page6*/
-.byte4	0x01C00000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page7*/
-#ifndef CONFIG_EZKIT
-.byte4	0x02000000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page8*/
-.byte4	0x02400000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page9*/
-.byte4	0x02800000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page10*/
-.byte4	0x02C00000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page11*/
-.byte4	0x03000000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page12*/
-.byte4	0x03400000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page13*/
-.byte4	0x03800000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page14*/
-#endif
-.byte4	0xffffffff;		/*end of section - termination*/
-
 /**********************************************************************
  *		PAGE DESCRIPTOR TABLE
  *
@@ -267,14 +196,8 @@ dpdt_table:
 .byte4        0x03C00000;
 .byte4        (SDRAM_DGENERIC);       /*SDRAM_Page15*/
 #endif
-.byte4	0x20200000;
-.byte4	(SDRAM_EBIU);	/* Async Memory Bank 2 (Secnd)*/
-.byte4	0x20100000;
-.byte4	(SDRAM_EBIU);	/* Async Memory Bank 1 (Prim B)*/
 .byte4	0x20000000;
 .byte4	(SDRAM_EBIU);	/* Async Memory Bank 0 (Prim A)*/
-.byte4	0x20300000;		/*Fix for Network*/
-.byte4  (SDRAM_EBIU);	/*Async Memory bank 3*/
 
 #ifdef CONFIG_STAMP
 .byte4	0x04000000;
diff --git a/include/asm-blackfin/cpu/cdefBF53x.h b/include/asm-blackfin/cpu/cdefBF53x.h
index db4eaa9..775a711 100644
--- a/include/asm-blackfin/cpu/cdefBF53x.h
+++ b/include/asm-blackfin/cpu/cdefBF53x.h
@@ -15,12 +15,20 @@
 	#include <asm/cpu/cdefBF532.h>
 #elif defined(__ADSPBF533__)
 	#include <asm/cpu/cdefBF533.h>
+	#include <asm/cpu/defBF533_extn.h>
+	#include <asm/cpu/bf533_serial.h>
+#elif defined(__ADSPBF537__)
+	#include <asm/cpu/cdefBF537.h>
+	#include <asm/cpu/defBF533_extn.h>
+	#include <asm/cpu/bf533_serial.h>
 #elif defined(__ADSPBF561__)
 	#include <asm/cpu/cdefBF561.h>
+	#include <asm/cpu/defBF533_extn.h>
+	#include <asm/cpu/bf533_serial.h>
 #elif defined(__ADSPBF535__)
 	#include <asm/cpu/cdefBF535.h>
 #elif defined(__AD6532__)
-	#include <sam/cpu/cdefAD6532.h>
+	#include <asm/cpu/cdefAD6532.h>
 #else
 	#if defined(__ADSPLPBLACKFIN__)
 		#include <asm/cpu/cdefBF532.h>
diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h
index 56a12f0..a0d7a65 100644
--- a/include/asm-blackfin/global_data.h
+++ b/include/asm-blackfin/global_data.h
@@ -49,6 +49,11 @@ typedef struct global_data {
 	unsigned long reloc_off;	/* Relocation Offset */
 	unsigned long env_addr;		/* Address  of Environment struct */
 	unsigned long env_valid;	/* Checksum of Environment valid? */
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+	unsigned long   post_log_word;  /* Record POST activities */
+	unsigned long   post_init_f_time;  /* When post_init_f started */
+#endif
+
 	void **jt;			/* jump table */
 } gd_t;
 
diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h
index 1ee050e..a2743a8 100644
--- a/include/asm-blackfin/hw_irq.h
+++ b/include/asm-blackfin/hw_irq.h
@@ -30,8 +30,14 @@
 
 #include <linux/config.h>
 #ifdef CONFIG_EZKIT533
-#include <asm/board/bf533_irq.h>
+#include <asm/cpu/bf533_irq.h>
+#endif
+#ifdef CONFIG_EZKIT561
+#include <asm/cpu/bf561_irq.h>
 #endif
 #ifdef CONFIG_STAMP
-#include <asm/board/bf533_irq.h>
+#include <asm/cpu/bf533_irq.h>
+#endif
+#ifdef CONFIG_BF537
+#include <asm/cpu/bf537_irq.h>
 #endif
diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h
index 5fbc5a3..c7bfc14 100644
--- a/include/asm-blackfin/irq.h
+++ b/include/asm-blackfin/irq.h
@@ -39,7 +39,7 @@
 #define _BLACKFIN_IRQ_H_
 
 #include <linux/config.h>
-#include <asm/cpu/bf533_irq.h>
+#include <asm/hw_irq.h>
 
 /*
  *   On the Blackfin, the interrupt structure allows remmapping of the hardware
diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h
index 1a13d90..3ea684c 100644
--- a/include/asm-blackfin/mem_init.h
+++ b/include/asm-blackfin/mem_init.h
@@ -111,6 +111,13 @@
 	#define SDRAM_CL	CL_2
 #endif
 
+#if (CONFIG_MEM_MT48LC16M8A2TG_75)
+	/*SDRAM INFORMATION: */
+	#define SDRAM_Tref      64       /* Refresh period in milliseconds   */
+	#define SDRAM_NRA       4096     /* Number of row addresses in SDRAM */
+	#define SDRAM_CL        CL_3
+#endif
+
 #if ( CONFIG_MEM_SIZE == 128 )
 	#define SDRAM_SIZE	EBSZ_128
 #endif
diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h
index ffd81d6..3b72e69 100644
--- a/include/asm-blackfin/string.h
+++ b/include/asm-blackfin/string.h
@@ -31,7 +31,8 @@
 
 #include <asm/setup.h>
 #include <asm/page.h>
-#include <asm/cpu/defBF533.h>
+#include <config.h>
+#include <asm/blackfin.h>
 
 #define __HAVE_ARCH_STRCPY
 #define __HAVE_ARCH_STRNCPY
diff --git a/lib_blackfin/bf533_linux.c b/lib_blackfin/bf533_linux.c
index 88b4da2..3a6a7d4 100644
--- a/lib_blackfin/bf533_linux.c
+++ b/lib_blackfin/bf533_linux.c
@@ -53,6 +53,8 @@ static char *make_command_line(void);
 
 extern image_header_t header;
 extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
+extern void flush_instruction_cache(void);
+extern void flush_data_cache(void);
 void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
 		    ulong addr, ulong * len_ptr, int verify)
 {
diff --git a/lib_blackfin/bf533_string.c b/lib_blackfin/bf533_string.c
index c8b1a3a..9eb9dc2 100644
--- a/lib_blackfin/bf533_string.c
+++ b/lib_blackfin/bf533_string.c
@@ -28,9 +28,12 @@
 #include <common.h>
 #include <asm/setup.h>
 #include <asm/page.h>
-#include <asm/cpu/defBF533.h>
+#include <config.h>
+#include <asm/blackfin.h>
 
 void *dma_memcpy(void *,const void *,size_t);
+extern void blackfin_icache_flush_range(unsigned long ,unsigned long );
+extern void blackfin_dcache_flush_range(unsigned long ,unsigned long );
 
 char *strcpy(char *dest, const char *src)
 {
@@ -128,16 +131,21 @@ void * memcpy(void * dest,const void *sr
 {
 	char *tmp = (char *) dest, *s = (char *) src;
 
+	unsigned long start, end, temp;
+	temp  = (unsigned long)tmp;
+	start = (unsigned long)src;
+	end   = (unsigned long)src + (unsigned long)count;
+	
 /* Turn off the cache, if destination in the L1 memory */
-	if ( (tmp >= (char *)L1_ISRAM) && (tmp < (char *)L1_ISRAM_END)
-		|| (tmp >= (char *)DATA_BANKA_SRAM) && (tmp < DATA_BANKA_SRAM_END)
-	    || (tmp >= (char *)DATA_BANKB_SRAM) && (tmp < DATA_BANKB_SRAM_END) ){
+	if ( ((temp >= L1_ISRAM) && (temp < L1_ISRAM_END))
+		|| ((temp >= DATA_BANKA_SRAM) && (temp < DATA_BANKA_SRAM_END))
+	    || ((temp >= DATA_BANKB_SRAM) && (temp < DATA_BANKB_SRAM_END)) ){
 			if(icache_status()){
-					blackfin_icache_flush_range(src, src+count);
+					blackfin_icache_flush_range(start, end);
 					icache_disable();
 			}
 			if(dcache_status()){
-					blackfin_dcache_flush_range(src, src+count);
+					blackfin_dcache_flush_range(start, end);
 					dcache_disable();
 			}
 			dma_memcpy(dest,src,count);
diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c
index 55d13fa..a8a04ee 100644
--- a/lib_blackfin/board.c
+++ b/lib_blackfin/board.c
@@ -35,8 +35,14 @@
 #include "blackfin_board.h"
 #include "../drivers/smc91111.h"
 
+#ifndef CFG_NO_FLASH
 extern flash_info_t flash_info[];
+#endif
 
+#ifdef CONFIG_SOFT_I2C
+static int init_func_i2c (void);
+void i2c_init (int, int);
+#endif
 
 static void mem_malloc_init(void)
 {
@@ -201,6 +207,13 @@ void board_init_r(gd_t * id, ulong dest_
 	mem_malloc_init();
 	malloc_bin_reloc();
 
+#ifdef CONFIG_SPI
+# if ! defined(CFG_ENV_IS_IN_EEPROM)
+	spi_init_f();
+# endif
+	spi_init_r();
+#endif
+
 	/* relocate environment function pointers etc. */
 	env_relocate();
 
@@ -231,6 +244,12 @@ void board_init_r(gd_t * id, ulong dest_
 		copy_filename(BootFile, s, sizeof(BootFile));
 	}
 #endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+        puts ("NAND:  ");
+        nand_init();            /* go init the NAND */
+#endif
+
 #if defined(CONFIG_MISC_INIT_R)
 	/* miscellaneous platform dependent initialisations */
 	misc_init_r();
diff --git a/lib_blackfin/cache.c b/lib_blackfin/cache.c
index 847278d..ae3544a 100644
--- a/lib_blackfin/cache.c
+++ b/lib_blackfin/cache.c
@@ -26,15 +26,26 @@
  */
 
 /* for now: just dummy functions to satisfy the linker */
-extern void blackfin_icache_range (unsigned long *, unsigned long *);
-extern void blackfin_dcache_range (unsigned long *, unsigned long *);
-void flush_cache (unsigned long dummy1, unsigned long dummy2)
+#include <config.h>
+#include <asm/blackfin.h>
+extern void blackfin_icache_flush_range(unsigned long ,unsigned long );
+extern void blackfin_dcache_flush_range(unsigned long ,unsigned long );
+extern int  icache_status(void);
+extern int  dcache_status(void);
+void flush_cache(unsigned long dummy1, unsigned long dummy2)
 {
-	if (icache_status ()) {
-		blackfin_icache_flush_range (dummy1, dummy1 + dummy2);
-	}
-	if (dcache_status ()) {
-		blackfin_dcache_flush_range (dummy1, dummy1 + dummy2);
-	}
+        if((dummy1>= L1_ISRAM) && (dummy1 < L1_ISRAM_END))
+                return;
+	if((dummy1>= DATA_BANKA_SRAM) && (dummy1 < DATA_BANKA_SRAM_END))
+		return;
+	if((dummy1>= DATA_BANKB_SRAM) && (dummy1 < DATA_BANKB_SRAM_END))
+		return;
+
+	if(icache_status()){
+		blackfin_icache_flush_range(dummy1,dummy1+dummy2);
+		}
+	if(dcache_status()){
+		blackfin_dcache_flush_range(dummy1,dummy1+dummy2);
+		}
 	return;
 }

