We should follow 'read->set/clr bit->write' flow for enable_fec_anatop_clock, otherwise we may overridden configuration before enable_fec_anatop_clock.
Signed-off-by: Peng Fan Peng.Fan@freescale.com Cc: Stefano Babic sbabic@denx.de Cc: Cc: Fabio Estevam fabio.estevam@freescale.com --- arch/arm/cpu/armv7/mx6/clock.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index ba6cc75..11efd12 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -535,6 +535,8 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) if (freq < ENET_25MHZ || freq > ENET_125MHZ) return -EINVAL;
+ reg = readl(&anatop->pll_enet); + if (fec_id == 0) { reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);