Hi Steve,
On Saturday 21 January 2006 02:59, Stephen Williams wrote:
In message dqrtqm$bcg$1@sea.gmane.org you wrote:
This patch adds to JSE support a probe for various plausible SDRAM configurations available for the board.
I know that this is board-specific code, but I tend to reject this patch anyway. Why don't you use the existing code to detet memory sizes or to test memory for errors?
Uh, because I can't find it? This board doesn't have an SPD bus, if that is what you mean.
Please take a look at cpu/ppc4xx/sdram.c. It handles right now only the first SDRAM bank (405 and DDR on 440) by defining "CONFIG_SDRAM_BANK0" in your board config file. This is done with memory size autodetection using the functions Wolfgang pointed out.
A few remarks: - We will add some additional defines in the near future to allow to configure further SDRAM parameters like CAS latency. With these setting the timing regs (TR1, RTR) will be generated depending on the SDRAM clock. - You would have to enhance the code for multiple SDRAM banks. - The config table "CFG_SDRAM_TABLE" has to be extended for 256MByte support.
Best regards, Stefan