17 Oct
2012
17 Oct
'12
5:39 p.m.
On Thu, Sep 13, 2012 at 12:38:16PM -0700, Tom Rini wrote:
From: Pankaj Bharadiya pankaj.bharadiya@ti.com
The endpoint rx count register value will be zero if it is read before receive packet ready bit (PERI_RXCSR:RXPKTRDY) is set.
Check for the receive packet ready bit (PERI_RXCSR:RXPKTRDY) before reading endpoint rx count register. Proceed with rx count read and FIFO read only if RXPKTRDY bit is set.
Signed-off-by: Pankaj Bharadiya pankaj.bharadiya@ti.com Signed-off-by: Tom Rini trini@ti.com
Applied to u-boot-ti/master, thanks!
--
Tom