The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes should be reset after the XAUI starts tranmitting alignment signals.
Signed-off-by: Timur Tabi timur@freescale.com --- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 10 ------ board/freescale/corenet_ds/eth_p4080.c | 40 ++++++++++++++++++++---- 2 files changed, 33 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 07e58ed..89ed5b4 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -504,9 +504,6 @@ void fsl_serdes_init(void) const char *srds_lpd_arg; size_t arglen; #endif -#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 - enum srds_prtcl device; -#endif #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */ #endif @@ -787,11 +784,4 @@ void fsl_serdes_init(void) SRDS_RSTCTL_SDPD); } #endif - -#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 - for (device = XAUI_FM1; device <= XAUI_FM2; device++) { - if (is_serdes_configured(device)) - __serdes_reset_rx(srds_regs, cfg, device); - } -#endif } diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index d4657f7..a724ffc 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -96,18 +96,43 @@ struct mii_dev *mii_dev_for_muxval(u32 muxval) #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 int board_phy_config(struct phy_device *phydev) { - /* - * If this is the 10G PHY, and we switched it to fiber, - * we need to reset the serdes link for SERDES9 - */ - if ((phydev->port == PORT_FIBRE) && (phydev->drv->uid == 0x00a19410)) { +#ifdef CONFIG_PHY_TERANETICS + extern struct phy_driver tn2020_driver; + + if (phydev->drv->uid == tn2020_driver.uid) { + unsigned long timeout = 1 * 1000; /* 1 seconds */ enum srds_prtcl device;
+ /* + * Wait for the XAUI to come out of reset. This is when it + * starts transmitting alignment signals. + */ + while (--timeout) { + int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1); + if (reg < 0) { + printf("TN2020: Error reading from PHY at " + "address %u\n", phydev->addr); + break; + } + /* + * Note that we've never actually seen + * MDIO_CTRL1_RESET set to 1. + */ + if ((reg & MDIO_CTRL1_RESET) == 0) + break; + udelay(1000); + } + + if (!timeout) { + printf("TN2020: Timeout waiting for PHY at address %u " + " to reset.\n", phydev->addr); + } + switch (phydev->addr) { - case 4: + case CONFIG_SYS_FM1_10GEC1_PHY_ADDR: device = XAUI_FM1; break; - case 0: + case CONFIG_SYS_FM2_10GEC1_PHY_ADDR: device = XAUI_FM2; break; default: @@ -116,6 +141,7 @@ int board_phy_config(struct phy_device *phydev)
serdes_reset_rx(device); } +#endif
return 0; }