The MINI2416 board is based on a Samsung's S3C2416 SoC and has 64MB DDR2 SDRAM, 256MB NAND Flash, a LAN9220 Ethernet Controller and a WM8731 Audio CODEC. This U-Boot port was implemented and tested on a unit bought to Boardcon (http://www.armdesigner.com/) but there are some other chinese providers that can supply it with a selectable NAND chip from 128MB to 1GB.
Signed-off-by: José Miguel Gonçalves jose.goncalves@inov.pt --- Changes for v2: - Coding style cleanup - Use of Use of clrbits_le32(), setbits_le32() and clrsetbits_le32() - Use of register bit macros instead of magic numbers - Use of serial and rtc drivers implemented for s3c24x0
Changes for v3: - Changed target name from u-boot-ubl.bin to u-boot-pad.bin - Removed magic numbers - Changes to support new SPL framework
Changes for v4: - None
Changes for v5: - Changed target name from u-boot-pad.bin to u-boot-with-spl.bin - Coding style cleanup - removal of TABS after #define (this is not detected by checkpatch.pl!) - Removal of #define CONFIG_SYS_BAUDRATE_TABLE as this in the defaults now --- MAINTAINERS | 4 + board/boardcon/mini2416/Makefile | 47 ++++++++ board/boardcon/mini2416/config.mk | 4 + board/boardcon/mini2416/mini2416.c | 104 ++++++++++++++++ board/boardcon/mini2416/mini2416_spl.c | 202 ++++++++++++++++++++++++++++++++ board/boardcon/mini2416/u-boot-spl.lds | 63 ++++++++++ boards.cfg | 1 + include/configs/mini2416.h | 202 ++++++++++++++++++++++++++++++++ 8 files changed, 627 insertions(+) create mode 100644 board/boardcon/mini2416/Makefile create mode 100644 board/boardcon/mini2416/config.mk create mode 100644 board/boardcon/mini2416/mini2416.c create mode 100644 board/boardcon/mini2416/mini2416_spl.c create mode 100644 board/boardcon/mini2416/u-boot-spl.lds create mode 100644 include/configs/mini2416.h
diff --git a/MAINTAINERS b/MAINTAINERS index c5a6f2f..80ad29e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -653,6 +653,10 @@ Fabio Estevam fabio.estevam@freescale.com mx53ard i.MX53 mx53smd i.MX53
+José Gonçalves jose.goncalves@inov.pt + + mini2416 ARM926EJS (S3C2416 SoC) + Daniel Gorsulowski daniel.gorsulowski@esd.eu
meesc ARM926EJS (AT91SAM9263 SoC) diff --git a/board/boardcon/mini2416/Makefile b/board/boardcon/mini2416/Makefile new file mode 100644 index 0000000..bf92ba1 --- /dev/null +++ b/board/boardcon/mini2416/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2012 INOV - INESC Inovacao +# Jose Goncalves jose.goncalves@inov.pt +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +ifdef CONFIG_SPL_BUILD +COBJS += mini2416_spl.o +else +COBJS += mini2416.o +endif + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/boardcon/mini2416/config.mk b/board/boardcon/mini2416/config.mk new file mode 100644 index 0000000..17d8166 --- /dev/null +++ b/board/boardcon/mini2416/config.mk @@ -0,0 +1,4 @@ +PAD_TO := 0x2000 +ifndef CONFIG_SPL_BUILD +ALL-y += $(obj)u-boot-with-spl.bin +endif diff --git a/board/boardcon/mini2416/mini2416.c b/board/boardcon/mini2416/mini2416.c new file mode 100644 index 0000000..b2c049b --- /dev/null +++ b/board/boardcon/mini2416/mini2416.c @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2012 INOV - INESC Inovacao + * Jose Goncalves jose.goncalves@inov.pt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/s3c24xx_cpu.h> + +#define SMBIDCY1_VAL 0 /* Idle Cycle */ +#define SMBWSTWR1_VAL 14 /* Write Wait State */ +#define SMBWSTOEN1_VAL 2 /* Output Enable Assertion Delay */ +#define SMBWSTWEN1_VAL 2 /* Write Enable Assertion Delay */ +#define SMBWSTRD1_VAL 14 /* Read Wait State */ + +DECLARE_GLOBAL_DATA_PTR; + +static void ether_if_init(void) +{ + /* Ethernet chip is on memory bank 1 */ + struct s3c24xx_smc *const smc = s3c24xx_get_base_smc(S3C24XX_SMC1); + struct s3c24xx_gpio *const gpio = s3c24xx_get_base_gpio(); + + /* Set bus timings */ + writel(SMBIDCY1_VAL, &smc->smbidcy); + writel(SMBWSTWR1_VAL, &smc->smbwstwr); + writel(SMBWSTOEN1_VAL, &smc->smbwstoen); + writel(SMBWSTWEN1_VAL, &smc->smbwstwen); + writel(SMBWSTRD1_VAL, &smc->smbwstrd); + + /* Init SMC control register */ + clrsetbits_le32(&smc->smbc, + (SMBC_RSMAVD_WR | SMBC_RSMAVD_RD | SMBC_MW_MASK | + SMBC_WAIT_POL), + (SMBC_DRNOWE | SMBC_DRNCS | SMBC_MW_16BIT | + SMBC_WAIT_EN | SMBC_RBLE)); + + /* Enable CS pin */ + setbits_le32(&gpio->gpacon, GPACON_NRCS1); +} + +int board_init(void) +{ + struct s3c24xx_gpio *const gpio = s3c24xx_get_base_gpio(); + + /* Turn LED on */ + clrbits_le32(&gpio->gpcdat, GPCDAT(5)); + + /* Init interface with Ethernet chip */ + ether_if_init(); + + /* Arch number of MINI2416 Board */ + gd->bd->bi_arch_number = MACH_TYPE_MINI2416; + + /* Address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + printf("\nBoard: MINI2416\n"); + return 0; +} +#endif + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} +#endif diff --git a/board/boardcon/mini2416/mini2416_spl.c b/board/boardcon/mini2416/mini2416_spl.c new file mode 100644 index 0000000..5abdb23 --- /dev/null +++ b/board/boardcon/mini2416/mini2416_spl.c @@ -0,0 +1,202 @@ +/* + * (C) Copyright 2012 INOV - INESC Inovacao + * Jose Goncalves jose.goncalves@inov.pt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <spl.h> +#include <version.h> +#include <nand.h> +#include <asm/io.h> +#include <asm/arch/s3c24xx_cpu.h> + +/* FCLK = 800 MHz, HCLK = 133 MHz, PCLK = 66 MHz */ +#define M_MDIV 400 +#define M_PDIV 3 +#define M_SDIV 1 +#define ARMDIV 1 +#define PREDIV 2 +#define HCLKDIV 1 +#define M_LTIME 0x0E10 + +/* EPLLclk = 96MHz */ +#define E_MDIV 32 +#define E_PDIV 1 +#define E_SDIV 2 +#define E_LTIME 0x1780 + +DECLARE_GLOBAL_DATA_PTR; + +static inline void asm_delay(ulong loops) +{ + asm volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0"(loops)); +} + +static inline void watchdog_disable(void) +{ + struct s3c24xx_watchdog *const watchdog = s3c24xx_get_base_watchdog(); + + writel(WTCON_DISABLE_VAL, &watchdog->wtcon); +} + +static void pinmux_init(void) +{ + struct s3c24xx_gpio *const gpio = s3c24xx_get_base_gpio(); + + /* Init LED pin and turn LED off (LED on GPC5) */ + clrsetbits_le32(&gpio->gpccon, GPCCON_MASK(5), GPCCON_OUTPUT(5)); + setbits_le32(&gpio->gpcdat, GPCDAT(5)); + + /* Init UART pins */ + clrsetbits_le32(&gpio->gphcon, GPHCON_MASK(0) | GPHCON_MASK(1) | + GPHCON_MASK(2) | GPHCON_MASK(3) | GPHCON_MASK(4) | + GPHCON_MASK(5) | GPHCON_MASK(6) | GPHCON_MASK(7), + GPHCON_TXD(0) | GPHCON_RXD(0) | GPHCON_TXD(1) | + GPHCON_RXD(1) | GPHCON_TXD(2) | GPHCON_RXD(2) | + GPHCON_TXD(3) | GPHCON_RXD(3)); + + /* Init NAND interface */ + setbits_le32(&gpio->gpacon, GPACON_CLE | GPACON_ALE | GPACON_NFWE | + GPACON_NFRE | GPACON_NRSTOUT | GPACON_NFCE); +} + +static void pll_init(void) +{ + struct s3c2416_sysctl *const sysctl = s3c2416_get_base_sysctl(); + + /* Configure clocks division ratio */ + clrsetbits_le32(&sysctl->clkdiv0, + CLKDIV0_ARMDIV_MASK | CLKDIV0_PREDIV_MASK | + CLKDIV0_HCLKDIV_MASK, + CLKDIV0_ARMDIV(ARMDIV) | CLKDIV0_PREDIV(PREDIV) | + CLKDIV0_HALFHCLK | CLKDIV0_PCLKDIV | + CLKDIV0_HCLKDIV(HCLKDIV)); + + /* Set MPLL lock time */ + writel(M_LTIME, &sysctl->lockcon0); + + /* Configure MPLL */ + writel(MPLLCON_MDIV(M_MDIV) | MPLLCON_PDIV(M_PDIV) | + PLLCON_SDIV(M_SDIV), &sysctl->mpllcon); + + /* Set EPLL lock time */ + writel(E_LTIME, &sysctl->lockcon1); + + /* Configure EPLL */ + writel(EPLLCON_MDIV(E_MDIV) | EPLLCON_PDIV(E_PDIV) | + PLLCON_SDIV(E_SDIV), &sysctl->epllcon); + + /* MSYSCLK = MPLL and ESYSCLK = EPLL */ + setbits_le32(&sysctl->clksrc, + CLKSRC_MSYSCLK_MPLL | CLKSRC_ESYSCLK_EPLL); +} + +static void dramctl_init(void) +{ + struct s3c24xx_dramctl *const dramctl = s3c24xx_get_base_dramctl(); + + /* Step 1: Init BANKCFG & BANKCON1 */ + writel(BANKCFG_VAL_DDR2, &dramctl->bankcfg); + writel(BANKCON1_VAL_DDR2, &dramctl->bankcon1); + + /* Step 2: Init BANKCON2 */ + writel(BANKCON2_VAL_DDR2, &dramctl->bankcon2); + + /* Step 3: Issue a PALL command */ + writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_PALL, &dramctl->bankcon1); + + /* Step 4: Issue a EMRS2 command */ + writel(BANKCON3_VAL_EMRS2, &dramctl->bankcon3); + writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_EMRS, &dramctl->bankcon1); + + /* Step 5: Issue a EMRS3 command */ + writel(BANKCON3_VAL_EMRS3, &dramctl->bankcon3); + writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_EMRS, &dramctl->bankcon1); + + /* Step 6: Issue a EMRS1 command */ + writel(BANKCON3_VAL_EMRS1, &dramctl->bankcon3); + writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_EMRS, &dramctl->bankcon1); + + /* Step 7: Issue a MRS command */ + writel(BANKCON3_VAL_MRS | BANKCON3_MRS_DLL_RESET, &dramctl->bankcon3); + writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_MRS, &dramctl->bankcon1); + + /* Step 8: Issue a PALL command */ + writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_PALL, &dramctl->bankcon1); + + /* Step 9: Write 0xFF into the refresh timer */ + writel(0xFF, &dramctl->refresh); + + /* Step 10: Wait more than 120 clocks */ + asm_delay(256); + + /* Step 11: Issue a MRS command */ + writel(BANKCON3_VAL_MRS, &dramctl->bankcon3); + writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_MRS, &dramctl->bankcon1); + + /* Step 12: Issue a EMRS1 command */ + writel(BANKCON3_VAL_EMRS1 | BANKCON3_EMRS1_OCD7 | BANKCON3_EMRS1_CAS3, + &dramctl->bankcon3); + writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_EMRS, &dramctl->bankcon1); + + writel(BANKCON3_VAL_EMRS1 | BANKCON3_EMRS1_CAS3, &dramctl->bankcon3); + writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_EMRS, &dramctl->bankcon1); + + /* Step 13: Write 0x87 into the refresh timer */ + writel(0x87, &dramctl->refresh); + + /* Step 14: Normal Mode */ + writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_NORMAL, &dramctl->bankcon1); +} + +#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT +#ifdef CONFIG_SPL_SERIAL_SUPPORT +void puts(const char *str) +{ + serial_puts(str); +} +#else +void puts(const char *str) +{ +} +#endif +#endif + +void spl_board_init(void) +{ + watchdog_disable(); + pinmux_init(); + pll_init(); + preloader_console_init(); + dramctl_init(); +} + +u32 spl_boot_device(void) +{ +#ifdef CONFIG_SPL_NAND_SIMPLE + puts("Loading U-Boot from NAND Flash...\n"); + return BOOT_DEVICE_NAND; +#else + puts("Unknown boot device\n"); + hang(); +#endif +} diff --git a/board/boardcon/mini2416/u-boot-spl.lds b/board/boardcon/mini2416/u-boot-spl.lds new file mode 100644 index 0000000..d339b0d --- /dev/null +++ b/board/boardcon/mini2416/u-boot-spl.lds @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2012 INOV - INESC Inovacao + * Jose Goncalves jose.goncalves@inov.pt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +MEMORY { .iram : ORIGIN = CONFIG_SPL_TEXT_BASE, \ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + CPUDIR/start.o (.text) + *(.text*) + } > .iram + + . = ALIGN(4); + .rodata : + { + *(SORT_BY_ALIGNMENT(.rodata*)) + } > .iram + + . = ALIGN(4); + .data : + { + *(SORT_BY_ALIGNMENT(.data*)) + } > .iram + + . = ALIGN(4); + _end = .; + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } >.sram +} diff --git a/boards.cfg b/boards.cfg index fdb84ad..823d5e6 100644 --- a/boards.cfg +++ b/boards.cfg @@ -185,6 +185,7 @@ omap730p2_cs0boot arm arm926ejs omap730p2 ti omap omap730p2_cs3boot arm arm926ejs omap730p2 ti omap omap730p2:CS3_BOOT edminiv2 arm arm926ejs - LaCie orion5x dkb arm arm926ejs - Marvell pantheon +mini2416 arm arm926ejs mini2416 boardcon s3c24xx spear300 arm arm926ejs spear300 spear spear spear3xx_evb:spear300 spear300_nand arm arm926ejs spear300 spear spear spear3xx_evb:spear300,nand spear300_usbtty arm arm926ejs spear300 spear spear spear3xx_evb:spear300,usbtty diff --git a/include/configs/mini2416.h b/include/configs/mini2416.h new file mode 100644 index 0000000..aa9ee6d --- /dev/null +++ b/include/configs/mini2416.h @@ -0,0 +1,202 @@ +/* + * (C) Copyright 2012 INOV - INESC Inovacao + * Jose Goncalves jose.goncalves@inov.pt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * SoC Configuration + */ +#define CONFIG_ARM926EJS /* ARM926EJS CPU Core */ +#define CONFIG_S3C24XX /* SAMSUNG S3C24XX Family */ +#define CONFIG_S3C2416 /* SAMSUNG S3C2416 SoC */ +#define CONFIG_SYS_CLK_FREQ 12000000 +#define CONFIG_SYS_HZ 1000 + +/* + * Memory Information + */ +#define CONFIG_SYS_IRAM_BASE 0x00000000 /* Steppingstone base address */ +#define CONFIG_SYS_IRAM_SIZE (8 << 10) /* 8KB of Steppingstone */ +#define CONFIG_SYS_IRAM_END (CONFIG_SYS_IRAM_BASE + CONFIG_SYS_IRAM_SIZE) + +#define CONFIG_SYS_SRAM_BASE 0x00002000 /* SRAM base address */ +#define CONFIG_SYS_SRAM_SIZE (56 << 10) /* 56KB of SRAM */ +#define CONFIG_SYS_SRAM_END (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE) + +#define CONFIG_SYS_SDRAM_BASE 0x30000000 /* DDR2 SDRAM base address */ +#define CONFIG_SYS_SDRAM_SIZE (64 << 20) /* 64MB of DDR2 SDRAM */ +#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE) + +/* + * Linux Interface + */ +#define MACH_TYPE_MINI2416 3850 +#define CONFIG_MACH_TYPE MACH_TYPE_MINI2416 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttySAC3,115200n8" +#define CONFIG_BOOTCOMMAND "" /* TBD */ + +/* + * SPL + */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x00000000 /* CONFIG_SYS_IRAM_BASE */ +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_IRAM_SIZE +#define CONFIG_SPL_BSS_START_ADDR CONFIG_SYS_SRAM_BASE +#define CONFIG_SPL_BSS_MAX_SIZE (CONFIG_SYS_SRAM_SIZE - (8 << 10)) +#define CONFIG_SPL_STACK CONFIG_SYS_SRAM_END /* 8KB for stack */ + +/* + * Monitor Interface + */ +#define CONFIG_SYS_PROMPT "MINI2416 # " +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING + +/* + * Command Definition + */ +#define CONFIG_SYS_NO_FLASH /* No NOR Flash */ +#include <config_cmd_default.h> +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MISC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING + +/* + * Miscellaneous Settings + */ +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20)) +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_END - (1 << 20)) +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_SYS_TEXT_BASE 0x33F00000 /* CONFIG_SYS_MONITOR_BASE */ +#define CONFIG_SYS_MALLOC_LEN (384 << 10) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MONITOR_BASE + +/* + * NAND Flash + */ +#ifdef CONFIG_CMD_NAND + +#define CONFIG_NAND_S3C24XX +#define CONFIG_S3C24XX_NAND_HWECC +#define CONFIG_SYS_NAND_BASE 0x4E000010 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* SPL NAND Driver */ +#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 4 +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55} +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_MAX_SIZE +#define CONFIG_SYS_NAND_U_BOOT_SIZE (CONFIG_SYS_MONITOR_LEN - \ + CONFIG_SPL_MAX_SIZE) + +#endif + +/* + * Serial Driver + */ +#define CONFIG_S3C24X0_SERIAL +#define CONFIG_SERIAL3 +#define CONFIG_BAUDRATE 115200 + +/* + * Ethernet + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_SMC911X +#define CONFIG_SMC911X_BASE 0x08000000 +#define CONFIG_SMC911X_16_BIT +#define CONFIG_ETHADDR FE:11:22:33:44:55 +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_IPADDR 192.168.0.10 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.0.1 +#define CONFIG_GATEWAYIP 192.168.0.1 +#endif + +/* + * RTC + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_S3C24X0 +#endif + +/* + * Environment + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +/* + * File System + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#endif + +#endif /* __CONFIG_H */