Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls.
Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64.
Signed-off-by: Chen-Yu Tsai wens@csie.org --- drivers/net/sun8i_emac.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 5fa1b4c170d7..0a98a04967da 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -616,6 +616,8 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+#ifdef CONFIG_MACH_SUNXI_H3_H5 + /* Only H3/H5 have clock controls for internal EPHY */ if (priv->use_internal_phy) { /* Set clock gating for ephy */ setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY)); @@ -623,6 +625,7 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) /* Deassert EPHY */ setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY)); } +#endif
/* Set clock gating for emac */ setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));