Hi,
In file ‘/u-boot-1.1.4/post/cache_8xx.S’, assembly
code is provided for the function ‘cache_post_test4’.
Comments have been added to describe what exactly happening
in the code.
I couldn’t find any instruction in the code which
flushes out the data cache even though it is mentioned in the comments.
The code snippet is appended for reference.
Am I missing something?
Regards,
Sachin Rane
8<
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/*
* turn on the data cache
* switch the data cache to write-back mode
* invalidate the data cache
* write the negative pattern to a cached area
* flush the data cache
* write the zero pattern to the area
* invalidate the data cache
* read the area
*
* The negative pattern must be read at the last step
*/
.global
cache_post_test4
cache_post_test4:
mflr r0
stw r0,
4(r1)
stwu r3,
-4(r1)
stwu r4,
-4(r1)
bl cache_post_ddisable
bl cache_post_dinvalidate
/*
Write the negative pattern to the test area */
lwz r0,
0(r1)
mtctr r0
li r0,
0xff
lwz r3,
4(r1)
subi r3,
r3, 1
1:
stbu r0,
1(r3)
bdnz 1b
bl cache_post_dwb
bl cache_post_dinvalidate
/*
Write the zero pattern to the test area */
lwz r0,
0(r1)
mtctr r0
li r0,
0
lwz r3,
4(r1)
subi r3,
r3, 1
1:
stbu r0,
1(r3)
bdnz 1b
bl cache_post_ddisable
bl cache_post_dinvalidate
/*
Read the test area */
lwz r0,
0(r1)
mtctr r0
lwz r4,
4(r1)
subi r4,
r4, 1
li r3,
0
1:
lbzu r0,
1(r4)
cmpli cr0,
r0, 0xff
beq 2f
li r3,
-1
b 3f
2:
bdnz 1b
3:
addi r1,
r1, 8
lwz r0,
4(r1)
mtlr r0
blr
cache_post_test5_1:
li r3,
0
cache_post_test5_2:
li r3,
-1
8<
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