This adds static register programming for PCIe and USB after memory init as required by Quark firmware writer guide. Although not doing this did not cause any malfunction, just do it for safety.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org
---
Changes in v5: None Changes in v3: None Changes in v2: - New patch to add PCIe/USB static register programming after memory init
arch/x86/cpu/quark/quark.c | 64 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/arch-quark/quark.h | 22 ++++++++++++ include/configs/galileo.h | 1 + 3 files changed, 87 insertions(+)
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index caa3875..934250b 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -223,6 +223,53 @@ void reset_cpu(ulong addr) x86_full_reset(); }
+static void quark_pcie_init(void) +{ + u32 val; + + /* PCIe upstream non-posted & posted request size */ + qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG, + CCFG_UPRS | CCFG_UNRS); + qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG, + CCFG_UPRS | CCFG_UNRS); + + /* PCIe packet fast transmit mode (IPF) */ + qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF); + qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF); + + /* PCIe message bus idle counter (SBIC) */ + qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val); + val |= MBC_SBIC; + qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val); + qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val); + val |= MBC_SBIC; + qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val); +} + +static void quark_usb_init(void) +{ + u32 bar; + + /* Change USB EHCI packet buffer OUT/IN threshold */ + qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar); + writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01); + + /* Disable USB device interrupts */ + qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar); + writel(0x7f, bar + USBD_INT_MASK); + writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK); + writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS); +} + +int arch_early_init_r(void) +{ + quark_pcie_init(); + + quark_usb_init(); + + return 0; +} + int cpu_mmc_init(bd_t *bis) { return pci_mmc_init("Quark SDHCI", mmc_supported, @@ -256,3 +303,20 @@ int arch_misc_init(void) { return pirq_init(); } + +void board_final_cleanup(void) +{ + struct quark_rcba *rcba; + u32 base, val; + + qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); + base &= ~MEM_BAR_EN; + rcba = (struct quark_rcba *)base; + + /* Initialize 'Component ID' to zero */ + val = readl(&rcba->esd); + val &= ~0xff0000; + writel(val, &rcba->esd); + + return; +} diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h index 5d81976..eb3afbf 100644 --- a/arch/x86/include/asm/arch-quark/quark.h +++ b/arch/x86/include/asm/arch-quark/quark.h @@ -88,6 +88,20 @@ /* 64KiB of RMU binary in flash */ #define RMU_BINARY_SIZE 0x10000
+/* PCIe Root Port Configuration Registers */ + +#define PCIE_RP_CCFG 0xd0 +#define CCFG_UPRS (1 << 14) +#define CCFG_UNRS (1 << 15) +#define CCFG_UNSD (1 << 23) +#define CCFG_UPSD (1 << 24) + +#define PCIE_RP_MPC2 0xd4 +#define MPC2_IPF (1 << 11) + +#define PCIE_RP_MBC 0xf4 +#define MBC_SBIC (3 << 16) + /* Legacy Bridge PCI Configuration Registers */ #define LB_GBA 0x44 #define LB_PM1BLK 0x48 @@ -100,6 +114,14 @@ #define LB_BC 0xd8 #define LB_RCBA 0xf0
+/* USB EHCI memory-mapped registers */ +#define EHCI_INSNREG01 0x94 + +/* USB device memory-mapped registers */ +#define USBD_INT_MASK 0x410 +#define USBD_EP_INT_STS 0x414 +#define USBD_EP_INT_MASK 0x418 + #ifndef __ASSEMBLY__
/* Root Complex Register Block */ diff --git a/include/configs/galileo.h b/include/configs/galileo.h index b7ec279..ba6c8f1 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -15,6 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_ARCH_MISC_INIT
/* ns16550 UART is memory-mapped in Quark SoC */