[U-Boot] [Patch v2, batch 2 16/23] T4/serdes: fix the actual serdes clock frequency

From: Roy Zang tie-fei.zang@freescale.com

The correct bit maps in BRDCFG2 are 0 1 2 3 4 5 6 7 S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0]

Signed-off-by: Roy Zang tie-fei.zang@freescale.com --- board/freescale/t4qds/t4qds.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c index a9cea0c..a84218c 100644 --- a/board/freescale/t4qds/t4qds.c +++ b/board/freescale/t4qds/t4qds.c @@ -586,7 +586,7 @@ int misc_init_r(void)

sw = QIXIS_READ(brdcfg[2]); for (i = 0; i < MAX_SERDES; i++) { - unsigned int clock = (sw >> (2 * i)) & 3; + unsigned int clock = (sw >> (6 - 2 * i)) & 3; switch (clock) { case 0: actual[i] = SRDS_PLLCR0_RFCK_SEL_100;