This board has not been converted to generic board by the deadline. Remove it.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/arm/mach-kirkwood/Kconfig | 4 - board/Marvell/mv88f6281gtw_ge/Kconfig | 12 -- board/Marvell/mv88f6281gtw_ge/MAINTAINERS | 6 - board/Marvell/mv88f6281gtw_ge/Makefile | 9 -- board/Marvell/mv88f6281gtw_ge/kwbimage.cfg | 149 ------------------------ board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c | 119 ------------------- board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h | 20 ---- configs/mv88f6281gtw_ge_defconfig | 7 -- include/configs/mv88f6281gtw_ge.h | 88 -------------- 9 files changed, 414 deletions(-) delete mode 100644 board/Marvell/mv88f6281gtw_ge/Kconfig delete mode 100644 board/Marvell/mv88f6281gtw_ge/MAINTAINERS delete mode 100644 board/Marvell/mv88f6281gtw_ge/Makefile delete mode 100644 board/Marvell/mv88f6281gtw_ge/kwbimage.cfg delete mode 100644 board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c delete mode 100644 board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h delete mode 100644 configs/mv88f6281gtw_ge_defconfig delete mode 100644 include/configs/mv88f6281gtw_ge.h
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 1ac99b8..ae29a11 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -7,9 +7,6 @@ choice config TARGET_OPENRD bool "Marvell OpenRD Board"
-config TARGET_MV88F6281GTW_GE - bool "MV88f6281GTW_GE Board" - config TARGET_RD6281A bool "RD6281A Board"
@@ -58,7 +55,6 @@ config SYS_SOC default "kirkwood"
source "board/Marvell/openrd/Kconfig" -source "board/Marvell/mv88f6281gtw_ge/Kconfig" source "board/Marvell/rd6281a/Kconfig" source "board/Marvell/dreamplug/Kconfig" source "board/Marvell/guruplug/Kconfig" diff --git a/board/Marvell/mv88f6281gtw_ge/Kconfig b/board/Marvell/mv88f6281gtw_ge/Kconfig deleted file mode 100644 index 00d7d1c..0000000 --- a/board/Marvell/mv88f6281gtw_ge/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MV88F6281GTW_GE - -config SYS_BOARD - default "mv88f6281gtw_ge" - -config SYS_VENDOR - default "Marvell" - -config SYS_CONFIG_NAME - default "mv88f6281gtw_ge" - -endif diff --git a/board/Marvell/mv88f6281gtw_ge/MAINTAINERS b/board/Marvell/mv88f6281gtw_ge/MAINTAINERS deleted file mode 100644 index 9c26ca7..0000000 --- a/board/Marvell/mv88f6281gtw_ge/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MV88F6281GTW_GE BOARD -M: Prafulla Wadaskar prafulla@marvell.com -S: Maintained -F: board/Marvell/mv88f6281gtw_ge/ -F: include/configs/mv88f6281gtw_ge.h -F: configs/mv88f6281gtw_ge_defconfig diff --git a/board/Marvell/mv88f6281gtw_ge/Makefile b/board/Marvell/mv88f6281gtw_ge/Makefile deleted file mode 100644 index e83bbf7..0000000 --- a/board/Marvell/mv88f6281gtw_ge/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mv88f6281gtw_ge.o diff --git a/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg b/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg deleted file mode 100644 index 9fa87ac..0000000 --- a/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg +++ /dev/null @@ -1,149 +0,0 @@ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1b1b1b9b - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000a00 # DDR Configuration register -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x38543000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x2202433D # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x0000002A # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x0000000D # DDR Address Control -# bit1-0: 01, Cs0width=x16 -# bit3-2: 11, Cs0size=1Gb -# bit5-4: 00, Cs2width=nonexistent -# bit7-6: 00, Cs1size =nonexistent -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000C52 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required - -DATA 0xFFD01420 0x00000046 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 1, DDR drive strenght reduced -# bit2: 1, DDR ODT control lsd enabled -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, enabled -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 1 , D2P Latency enabled -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x07, Size (i.e. 128MB) - -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low) -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 - -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 01, ODT1 active NEVER! -# bit31-4: zero, required - -DATA 0xFFD0149C 0x0000E811 # CPU ODT Control -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 -# bit11-10:1, DQ_ODTSel. ODT select turned on - -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c deleted file mode 100644 index ef08ad8..0000000 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Maintainer : Prafulla Wadaskar prafulla@marvell.com - * - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include <asm/arch/cpu.h> -#include <asm/arch/soc.h> -#include <asm/arch/mpp.h> -#include "mv88f6281gtw_ge.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* - * default gpio configuration - * There are maximum 64 gpios controlled through 2 sets of registers - * the below configuration configures mainly initial LED status - */ - mvebu_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW, - MV88F6281GTW_GE_OE_VAL_HIGH, - MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - static const u32 kwmpp_config[] = { - MPP0_SPI_SCn, - MPP1_SPI_MOSI, - MPP2_SPI_SCK, - MPP3_SPI_MISO, - MPP4_GPIO, - MPP5_GPO, - MPP6_SYSRST_OUTn, - MPP7_SPI_SCn, - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_GPO, - MPP13_GPIO, - MPP14_GPIO, - MPP15_GPIO, - MPP16_GPIO, - MPP17_GPIO, - MPP18_GPO, - MPP19_GPO, - MPP20_GPIO, - MPP21_GPIO, - MPP22_GPIO, - MPP23_GPIO, - MPP24_GPIO, - MPP25_GPIO, - MPP26_GPIO, - MPP27_GPIO, - MPP28_GPIO, - MPP29_GPIO, - MPP30_GPIO, - MPP31_GPIO, - MPP32_GPIO, - MPP33_GPIO, - MPP34_GPIO, - MPP35_GPIO, - MPP36_GPIO, - MPP37_GPIO, - MPP38_GPIO, - MPP39_GPIO, - MPP40_GPIO, - MPP41_GPIO, - MPP42_GPIO, - MPP43_GPIO, - MPP44_GPIO, - MPP45_GPIO, - MPP46_GPIO, - MPP47_GPIO, - MPP48_GPIO, - MPP49_GPIO, - 0 - }; - kirkwood_mpp_conf(kwmpp_config, NULL); - return 0; -} - -int board_init(void) -{ - /* - * arch number of board - */ - gd->bd->bi_arch_number = MACH_TYPE_MV88F6281GTW_GE; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - - return 0; -} - -#ifdef CONFIG_MV88E61XX_SWITCH -void reset_phy(void) -{ - /* configure and initialize switch */ - struct mv88e61xx_config swcfg = { - .name = "egiga0", - .vlancfg = MV88E61XX_VLANCFG_ROUTER, - .rgmii_delay = MV88E61XX_RGMII_DELAY_EN, - .led_init = MV88E61XX_LED_INIT_EN, - .mdip = MV88E61XX_MDIP_REVERSE, - .portstate = MV88E61XX_PORTSTT_FORWARDING, - .cpuport = (1 << 5), - .ports_enabled = 0x3f - }; - - mv88e61xx_switch_initialize(&swcfg); -} -#endif /* CONFIG_MV88E61XX_SWITCH */ diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h deleted file mode 100644 index 447e227..0000000 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MV88F6281GTW_GE_H -#define __MV88F6281GTW_GE_H - -#define MV88F6281GTW_GE_OE_LOW (~((1 << 7) | (1 << 12) \ - |(1 << 20) | (1 << 21))) /*enable GLED,RLED */ -#define MV88F6281GTW_GE_OE_HIGH (~((1 << 4)|(1 << 6)|(1 << 7)|(1 << 12) \ - |(1 << 13)|(1 << 16)|(1 << 17))) -#define MV88F6281GTW_GE_OE_VAL_LOW (1 << 20) /*make GLED on */ -#define MV88F6281GTW_GE_OE_VAL_HIGH ((1 << 6)|(1 << 13)|(1 << 16)|(1 << 17)) - - -#endif /* __MV88F6281GTW_GE_H */ diff --git a/configs/mv88f6281gtw_ge_defconfig b/configs/mv88f6281gtw_ge_defconfig deleted file mode 100644 index 8988734..0000000 --- a/configs/mv88f6281gtw_ge_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_ARM=y -CONFIG_KIRKWOOD=y -CONFIG_TARGET_MV88F6281GTW_GE=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SPI_FLASH=y diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h deleted file mode 100644 index 45a4a75..0000000 --- a/include/configs/mv88f6281gtw_ge.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_MV88F6281GTW_GE_H -#define _CONFIG_MV88F6281GTW_GE_H - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nMarvell-MV88F6281GTW_GE" - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_MACH_MV88F6281GTW_GE /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FAT -#define CONFIG_CMD_PING -#define CONFIG_CMD_SF -#define CONFIG_CMD_USB - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* Unwanted stuffs from mv-common.h */ -#undef CONFIG_CMD_EXT2 -#undef CONFIG_CMD_JFFS2 -#undef CONFIG_CMD_FAT -#undef CONFIG_CMD_UBI -#undef CONFIG_CMD_UBIFS -#undef CONFIG_RBTREE - -/* - * Environment variables configurations - */ -#ifdef CONFIG_SPI_FLASH -#define CONFIG_ENV_IS_IN_SPI_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */ -#else -#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ -#endif -#define CONFIG_ENV_SIZE 0x1000 /* 4k */ -#define CONFIG_ENV_ADDR 0x30000 -#define CONFIG_ENV_OFFSET 0x30000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "${x_bootcmd_usb}; bootm 0x6400000;" - -#define CONFIG_MTDPARTS "spi0.0:512k(uboot)," \ - "512k@512k(psm),2m@1m(kernel),13m@3m(rootfs)\0" - -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \ - "x_bootcmd_kernel=cp.b 0xE8100000 0x6400000 0x200000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=/dev/mtdblock3 ro rootfstype=squashfs\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_MV88E61XX_SWITCH /* Enable mv88e61xx switch driver */ -#endif /* CONFIG_CMD_NET */ - -#endif /* _CONFIG_MV88F6281GTW_GE_H */