Hi Michael,
On Fri, 2022-03-11 at 08:57 +0100, Michael Nazzareno Trimarchi wrote:
Caution: EXT Email
Hi
On Tue, Mar 8, 2022 at 7:42 AM Ye Li ye.li@nxp.com wrote:
The change in commit c1af358 (imx: mx6ull: fix REFTOP_VBGADJ setting) is not correct. According to latest i.MX6ULL fuse table, the REFTOP_TRIM[2:0] fuse is defined as below. So the previous codes are correct, only need to fix the comments.
Set the REFTOP_VBGADJ field in PMU_MISC0 register based on the REFTOP_TRIM fuse: '000" - set REFTOP_VBGADJ[2:0] to 3'b000 '001" - set REFTOP_VBGADJ[2:0] to 3'b001 '010" - set REFTOP_VBGADJ[2:0] to 3'b010 '011" - set REFTOP_VBGADJ[2:0] to 3'b011 '100" - set REFTOP_VBGADJ[2:0] to 3'b100 '101" - set REFTOP_VBGADJ[2:0] to 3'b101 '110" - set REFTOP_VBGADJ[2:0] to 3'b110 '111" - set REFTOP_VBGADJ[2:0] to 3'b111
Signed-off-by: Ye Li ye.li@nxp.com
arch/arm/mach-imx/mx6/soc.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach- imx/mx6/soc.c index 03d8fd7..bb7dc42 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -394,23 +394,21 @@ static void init_bandgap(void) /* * On i.MX6ULL,we need to set VBGADJ bits according to the * REFTOP_TRIM[3:0] in fuse table - * 000 - set REFTOP_VBGADJ[2:0] to 3b'110, - * 110 - set REFTOP_VBGADJ[2:0] to 3b'000, - * 001 - set REFTOP_VBGADJ[2:0] to 3b'001, - * 010 - set REFTOP_VBGADJ[2:0] to 3b'010, - * 011 - set REFTOP_VBGADJ[2:0] to 3b'011, - * 100 - set REFTOP_VBGADJ[2:0] to 3b'100, - * 101 - set REFTOP_VBGADJ[2:0] to 3b'101, - * 111 - set REFTOP_VBGADJ[2:0] to 3b'111, + * 000 - set REFTOP_VBGADJ[2:0] to 3'b000 + * 001 - set REFTOP_VBGADJ[2:0] to 3'b001 + * 010 - set REFTOP_VBGADJ[2:0] to 3'b010 + * 011 - set REFTOP_VBGADJ[2:0] to 3'b011 + * 100 - set REFTOP_VBGADJ[2:0] to 3'b100 + * 101 - set REFTOP_VBGADJ[2:0] to 3'b101 + * 110 - set REFTOP_VBGADJ[2:0] to 3'b110 + * 111 - set REFTOP_VBGADJ[2:0] to 3'b111 */ if (is_mx6ull()) { - static const u32 map[] = {6, 1, 2, 3, 4, 5, 0, 7};
val = readl(&fuse->mem0); val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT; val &= 0x7;
- writel(map[val] << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT, + writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT, &anatop->ana_misc0_set); }
If this is the case. I have the impression there are a lot of cpus that have this fuse not set during manufacturing.
Most of iMX6 series don't need to program this fuse, but 6ull is a exception due to different process used. if your 6ull don't have the fuse programmed, please contact NXP support team.
If this can happen if we have devices in the field already programmed that they do any temperature evaluation for thermal framework the calculation start to be different and they can have impact on their device
I don't understand this. Anyway, both NXP manufacturing and SW need to follow the fuse value definition.
Best regards, Ye Li
Michael
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2.7.4
-- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael@amarulasolutions.com __________________________________
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