Add basic support for the Nuvoton NPCM750 BMC
Signed-off-by: Jim Liu JJLIU0@nuvoton.com --- arch/arm/Kconfig | 8 ++ arch/arm/Makefile | 1 + arch/arm/include/asm/arch-npcm7xx/cpu.h | 28 ++++++ arch/arm/include/asm/arch-npcm7xx/gcr.h | 64 +++++++++++++ arch/arm/include/asm/arch-npcm7xx/rst.h | 37 ++++++++ arch/arm/mach-nuvoton/Kconfig | 34 +++++++ arch/arm/mach-nuvoton/Makefile | 1 + arch/arm/mach-nuvoton/npcm7xx/Kconfig | 18 ++++ arch/arm/mach-nuvoton/npcm7xx/Makefile | 2 + arch/arm/mach-nuvoton/npcm7xx/cpu.c | 67 ++++++++++++++ .../arm/mach-nuvoton/npcm7xx/l2_cache_pl310.c | 30 ++++++ .../npcm7xx/l2_cache_pl310_init.S | 89 ++++++++++++++++++ arch/arm/mach-nuvoton/npcm7xx/reset.c | 46 ++++++++++ board/nuvoton/poleg/Kconfig | 31 +++++++ board/nuvoton/poleg/Makefile | 1 + board/nuvoton/poleg/poleg_evb.c | 52 +++++++++++ include/configs/poleg.h | 77 ++++++++++++++++ .../dt-bindings/reset/nuvoton,npcm7xx-reset.h | 91 +++++++++++++++++++ 18 files changed, 677 insertions(+) create mode 100644 arch/arm/include/asm/arch-npcm7xx/cpu.h create mode 100644 arch/arm/include/asm/arch-npcm7xx/gcr.h create mode 100644 arch/arm/include/asm/arch-npcm7xx/rst.h create mode 100644 arch/arm/mach-nuvoton/Kconfig create mode 100644 arch/arm/mach-nuvoton/Makefile create mode 100644 arch/arm/mach-nuvoton/npcm7xx/Kconfig create mode 100644 arch/arm/mach-nuvoton/npcm7xx/Makefile create mode 100644 arch/arm/mach-nuvoton/npcm7xx/cpu.c create mode 100644 arch/arm/mach-nuvoton/npcm7xx/l2_cache_pl310.c create mode 100644 arch/arm/mach-nuvoton/npcm7xx/l2_cache_pl310_init.S create mode 100644 arch/arm/mach-nuvoton/npcm7xx/reset.c create mode 100644 board/nuvoton/poleg/Kconfig create mode 100644 board/nuvoton/poleg/Makefile create mode 100644 board/nuvoton/poleg/poleg_evb.c create mode 100644 include/configs/poleg.h create mode 100644 include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4567c183fb..45ab2793b2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -922,6 +922,12 @@ config ARCH_NEXELL select DM select GPIO_EXTRA_HEADER
+config ARCH_NPCM + bool "Support Nuvoton SoCs" + select DM + select OF_CONTROL + imply CMD_DM + config ARCH_APPLE bool "Apple SoCs" select ARM64 @@ -2196,6 +2202,8 @@ source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-nexell/Kconfig"
+source "arch/arm/mach-nuvoton/Kconfig" + source "board/armltd/total_compute/Kconfig"
source "board/bosch/shc/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ad757e982e..ad29f2418e 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -72,6 +72,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MVEBU) += mvebu machine-$(CONFIG_ARCH_NEXELL) += nexell +machine-$(CONFIG_ARCH_NPCM) += nuvoton machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 machine-$(CONFIG_ARCH_ORION5X) += orion5x machine-$(CONFIG_ARCH_OWL) += owl diff --git a/arch/arm/include/asm/arch-npcm7xx/cpu.h b/arch/arm/include/asm/arch-npcm7xx/cpu.h new file mode 100644 index 0000000000..2189ad2fd3 --- /dev/null +++ b/arch/arm/include/asm/arch-npcm7xx/cpu.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2021 Nuvoton Technology Corp. + */ + +#ifndef __NPCMX50_CPU_H_ +#define __NPCMX50_CPU_H_ + +#define NPCM750_GCR_BA 0xF0800000 +#define NPCM750_CLK_BA 0xF0801000 +#define NPCM750_GPIO_BA 0xF0010000 + +#ifndef __ASSEMBLY__ + +#define NPCM750_BASE(device, base) \ +static inline unsigned long __attribute__((no_instrument_function)) \ + npcm_get_base_##device(void) \ +{ \ + return NPCM750_##base; \ +} + +NPCM750_BASE(gcr, GCR_BA) +NPCM750_BASE(clk, CLK_BA) +NPCM750_BASE(gpio, GPIO_BA) + +#endif + +#endif diff --git a/arch/arm/include/asm/arch-npcm7xx/gcr.h b/arch/arm/include/asm/arch-npcm7xx/gcr.h new file mode 100644 index 0000000000..cbeca27d77 --- /dev/null +++ b/arch/arm/include/asm/arch-npcm7xx/gcr.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __NPCM750_GCR_H_ +#define __NPCM750_GCR_H_ + +/* On-Chip POLEG NPCM750 VERSIONS */ +#define POLEG_Z1 0x00A92750 +#define POLEG_A1 0x04A92750 +#define POLEG_NPCM750 0x00000000 +#define POLEG_NPCM730 0x00300395 +#define POLEG_NPCM710 0x00200380 + +#define PWRON_SECEN 7 /* STRAP8 */ + +struct npcm_gcr { + unsigned int pdid; + unsigned int pwron; + unsigned char res1[0x4]; + unsigned int mfsel1; + unsigned int mfsel2; + unsigned int miscpe; + unsigned char res2[0x20]; + unsigned int spswc; + unsigned int intcr; + unsigned int intsr; + unsigned char res3[0xc]; + unsigned int hifcr; + unsigned int sd1irv1; + unsigned int sd1irv2; + unsigned char res4[0x4]; + unsigned int intcr2; + unsigned int mfsel3; + unsigned int srcnt; + unsigned int ressr; + unsigned int rlockr1; + unsigned int flockr1; + unsigned int dscnt; + unsigned int mdlr; + unsigned char res5[0x18]; + unsigned int davclvlr; + unsigned int intcr3; + unsigned char res6[0xc]; + unsigned int vsintr; + unsigned int mfsel4; + unsigned int sd2irv1; + unsigned int sd2irv2; + unsigned char res7[0x8]; + unsigned int cpbpntr; + unsigned char res8[0x8]; + unsigned int cpctl; + unsigned int cp2bst; + unsigned int b2cpnt; + unsigned int cppctl; + unsigned int i2csegsel; + unsigned int i2csegctl; + unsigned int vsrcr; + unsigned int mlockr; + unsigned char res9[0x4c]; + unsigned int scrpad; + unsigned int usb1phyctl; + unsigned int usb2phyctl; +}; + +#endif diff --git a/arch/arm/include/asm/arch-npcm7xx/rst.h b/arch/arm/include/asm/arch-npcm7xx/rst.h new file mode 100644 index 0000000000..2545d9ed20 --- /dev/null +++ b/arch/arm/include/asm/arch-npcm7xx/rst.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _NPCM_RST_H_ +#define _NPCM_RST_H_ + +#define WTCR0_REG 0xF000801C +#define WTCR_WTR BIT(0) +#define WTCR_WTRE BIT(1) +#define WTCR_WTE BIT(7) + +enum reset_type { + PORST_TYPE = 0x01, + CORST_TYPE = 0x02, + WD0RST_TYPE = 0x03, + SWR1ST_TYPE = 0x04, + SWR2ST_TYPE = 0x05, + SWR3ST_TYPE = 0x06, + SWR4ST_TYPE = 0x07, + WD1RST_TYPE = 0x08, + WD2RST_TYPE = 0x09, + UNKNOWN_TYPE = 0x10, +}; + +#define PORST BIT(31) +#define CORST BIT(30) +#define WD0RST BIT(29) +#define SW1RST BIT(28) +#define SW2RST BIT(27) +#define SW3RST BIT(26) +#define TIPRST BIT(25) +#define WD1RST BIT(24) +#define WD2RST BIT(23) + +enum reset_type npcm7xx_reset_reason(void); + +#endif + diff --git a/arch/arm/mach-nuvoton/Kconfig b/arch/arm/mach-nuvoton/Kconfig new file mode 100644 index 0000000000..5f0128a9ab --- /dev/null +++ b/arch/arm/mach-nuvoton/Kconfig @@ -0,0 +1,34 @@ +if ARCH_NPCM + +config SYS_ARCH + default "arm" + +config SYS_TEXT_BASE + default 0x8000 + +choice + prompt "Nuvoton SoC select" + default ARCH_NPCM8XX + +config ARCH_NPCM8XX + bool "Support Nuvoton NPCM8xx SoC" + select ARM64 + help + General support for NPCM8xx BMC (Arbel). + Nuvoton NPCM8xx BMC is based on the Cortex A35. + +config ARCH_NPCM7xx + bool "Support Nuvoton NPCM7xx SoC" + select CPU_V7A + select OF_CONTROL + select DM + help + General support for NPCM7xx BMC (Poleg). + Nuvoton NPCM7xx BMC is based on the Cortex A9. + + +endchoice + +source "arch/arm/mach-nuvoton/npcm7xx/Kconfig" + +endif diff --git a/arch/arm/mach-nuvoton/Makefile b/arch/arm/mach-nuvoton/Makefile new file mode 100644 index 0000000000..8a1572b4f0 --- /dev/null +++ b/arch/arm/mach-nuvoton/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_NPCM7xx) += npcm7xx/ diff --git a/arch/arm/mach-nuvoton/npcm7xx/Kconfig b/arch/arm/mach-nuvoton/npcm7xx/Kconfig new file mode 100644 index 0000000000..6fd37ce367 --- /dev/null +++ b/arch/arm/mach-nuvoton/npcm7xx/Kconfig @@ -0,0 +1,18 @@ +if ARCH_NPCM7xx + +config SYS_CPU + default "armv7" + +config SYS_SOC + default "npcm7xx" + +config TARGET_POLEG + bool "NPCM POLEG board" + +config SYS_MEM_TOP_HIDE + hex "Reserved TOP memory" + default 0x03000000 + +source "board/nuvoton/poleg/Kconfig" + +endif diff --git a/arch/arm/mach-nuvoton/npcm7xx/Makefile b/arch/arm/mach-nuvoton/npcm7xx/Makefile new file mode 100644 index 0000000000..46e48018a0 --- /dev/null +++ b/arch/arm/mach-nuvoton/npcm7xx/Makefile @@ -0,0 +1,2 @@ +obj-y = reset.o +obj-$(CONFIG_TARGET_POLEG) += cpu.o l2_cache_pl310_init.o l2_cache_pl310.o diff --git a/arch/arm/mach-nuvoton/npcm7xx/cpu.c b/arch/arm/mach-nuvoton/npcm7xx/cpu.c new file mode 100644 index 0000000000..7872695690 --- /dev/null +++ b/arch/arm/mach-nuvoton/npcm7xx/cpu.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Nuvoton Technology Corp. + */ + +#include <common.h> +#include <cpu_func.h> +#include <asm/armv7.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/gcr.h> + +int print_cpuinfo(void) +{ + struct npcm_gcr *gcr = (struct npcm_gcr *)npcm_get_base_gcr(); + unsigned int id, mdlr; + + mdlr = readl(&gcr->mdlr); + + printf("CPU: "); + + switch (mdlr) { + case POLEG_NPCM750: + printf("NPCM750 "); + break; + case POLEG_NPCM730: + printf("NPCM730 "); + break; + case POLEG_NPCM710: + printf("NPCM710 "); + break; + default: + printf("NPCM7XX "); + break; + } + + id = readl(&gcr->pdid); + switch (id) { + case POLEG_Z1: + printf("Z1 is no supported! @ "); + break; + case POLEG_A1: + printf("A1 @ "); + break; + default: + printf("Unknown\n"); + break; + } + + return 0; +} + +void s_init(void) +{ + /* Invalidate L2 cache in lowlevel_init */ + v7_outer_cache_inval_all(); +} + +void enable_caches(void) +{ + dcache_enable(); +} + +void disable_caches(void) +{ + dcache_disable(); +} diff --git a/arch/arm/mach-nuvoton/npcm7xx/l2_cache_pl310.c b/arch/arm/mach-nuvoton/npcm7xx/l2_cache_pl310.c new file mode 100644 index 0000000000..805e13e863 --- /dev/null +++ b/arch/arm/mach-nuvoton/npcm7xx/l2_cache_pl310.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Nuvoton Technology Corp. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/pl310.h> + +void l2_pl310_init(void); +void set_pl310_ctrl(u32 enable); + +void set_pl310_ctrl(u32 enable) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + + writel(enable, &pl310->pl310_ctrl); +} + +void v7_outer_cache_enable(void) +{ + l2_pl310_init(); + + set_pl310_ctrl(1); +} + +void v7_outer_cache_disable(void) +{ + set_pl310_ctrl(0); +} diff --git a/arch/arm/mach-nuvoton/npcm7xx/l2_cache_pl310_init.S b/arch/arm/mach-nuvoton/npcm7xx/l2_cache_pl310_init.S new file mode 100644 index 0000000000..8f4124b64d --- /dev/null +++ b/arch/arm/mach-nuvoton/npcm7xx/l2_cache_pl310_init.S @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2021 Nuvoton Technology Corp. + */ + +.align 5 + +#include <linux/linkage.h> + +#ifndef CONFIG_SYS_L2CACHE_OFF + +ENTRY(l2_pl310_init) + + + @------------------------------------------------------------------ + @ L2CC (PL310) Initialization + @------------------------------------------------------------------ + @ In this example PL310 PA = VA. The memory was marked as Device memory + @ in previous stages when defining CORE0 private address space + LDR r0, =0xF03FC000 @ A9_BASE_ADDR + + @ Disable L2 Cache controller just in case it is already on + LDR r1, =0x0 + STR r1, [r0,#0x100] + + @ Set aux cntrl + @ Way size = 32KB + @ Way = 16 + LDR r1, =0x02050000 + ORR r1, r1, #(1 << 29) @ Instruction prefetch enable + ORR r1, r1, #(1 << 28) @ Data prefetch enable + ORR r1, r1, #(1 << 22) @ cache replacement policy + STR r1, [r0,#0x104] @ auxilary control reg at offset 0x104 + + @ Set tag RAM latency + @ 1 cycle RAM write access latency + @ 1 cycle RAM read access latency + @ 1 cycle RAM setup latency + LDR r1, =0x00000000 + STR r1, [r0,#0x108] @ tag ram control reg at offset 0x108 + + @ Set Data RAM latency + @ 1 cycle RAM write access latency + @ 2 cycles RAM read access latency + @ 1 cycle RAM setup latency + LDR r1, =0x00000000 + STR r1, [r0,#0x10C] @ data ram control reg at offset 0x108 + + @Cache maintenance - invalidate 16 ways (0xffff) - base offset 0x77C + LDR r1, =0xFFFF + STR r1, [r0,#0x77C] @ invalidate by way register at offset 0x77C + poll_invalidate: + LDR r1, [r0,#0x77C] @ invalidate by way register at offset 0x77C + TST r1, #1 + BNE poll_invalidate + + /* + @ Enable Event Counter Control Register. Reset counter 0 and 1 values + LDR r1, =0x007 + STR r1, [r0,#0x200] + + @ Counter 1. Count Drhit event + LDR r1, =0x008 + STR r1, [r0,#0x204] + + @ Counter 0. Count Dwhit event + LDR r1, =0x010 + STR r1, [r0,#0x208] + */ + + @ Ensure L2 remains disabled for the time being + LDR r1, =0x0 + STR r1, [r0,#0x100] + + MRC p15, 4, r0, c15, c0, 0 @ Read periph base address + @ SCU offset from base of private peripheral space = 0x000 + + LDR r1, [r0, #0x0] @ Read the SCU Control Register + ORR r1, r1, #0x1 @ Set bit 0 (The Enable bit) + STR r1, [r0, #0x0] @ Write back modifed value + + BX lr + + + +ENDPROC(l2_pl310_init) + + +#endif diff --git a/arch/arm/mach-nuvoton/npcm7xx/reset.c b/arch/arm/mach-nuvoton/npcm7xx/reset.c new file mode 100644 index 0000000000..74f925f67b --- /dev/null +++ b/arch/arm/mach-nuvoton/npcm7xx/reset.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Nuvoton Technology Corp. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/rst.h> +#include <asm/arch/gcr.h> +#include <asm/arch/cpu.h> + +void reset_cpu(ulong ignored) +{ + /* Generate a watchdog0 reset */ + writel(WTCR_WTR | WTCR_WTRE | WTCR_WTE, WTCR0_REG); + while (1) + ; +} + +void reset_misc(void) +{ + writel(readl(0xf0800060) & ~(1 << 21), 0xf0800060); +} + +enum reset_type npcm7xx_reset_reason(void) +{ + struct npcm_gcr *gcr = (struct npcm_gcr *)npcm_get_base_gcr(); + enum reset_type type = UNKNOWN_TYPE; + u32 value = readl(&gcr->ressr); + + if (value == 0) + value = ~readl(&gcr->intcr2); + + if (value & CORST) + type = CORST_TYPE; + if (value & WD0RST) + type = WD0RST_TYPE; + if (value & WD1RST) + type = WD1RST_TYPE; + if (value & WD2RST) + type = WD2RST_TYPE; + if (value & PORST) + type = PORST_TYPE; + + return type; +} diff --git a/board/nuvoton/poleg/Kconfig b/board/nuvoton/poleg/Kconfig new file mode 100644 index 0000000000..b1deef774f --- /dev/null +++ b/board/nuvoton/poleg/Kconfig @@ -0,0 +1,31 @@ +if TARGET_POLEG + +config SYS_BOARD + default "poleg" + +config SYS_VENDOR + default "nuvoton" + +config SYS_CONFIG_NAME + default "poleg" + +config NIST_VERSION_ADDR + hex "Linux NIST version address" + default 0x0 + help + The address of the Linux NIST version, which should be identical + to the u-boot version. + +choice + prompt "Target board select" + default TARGET_POLEG_EVB + +config TARGET_POLEG_EVB + bool "Poleg EVB" + +config TARGET_POLEG_RUNBMC + bool "Poleg RunBMC" + +endchoice + +endif diff --git a/board/nuvoton/poleg/Makefile b/board/nuvoton/poleg/Makefile new file mode 100644 index 0000000000..377433d60a --- /dev/null +++ b/board/nuvoton/poleg/Makefile @@ -0,0 +1 @@ +obj-y := poleg_evb.o diff --git a/board/nuvoton/poleg/poleg_evb.c b/board/nuvoton/poleg/poleg_evb.c new file mode 100644 index 0000000000..4c455be4ad --- /dev/null +++ b/board/nuvoton/poleg/poleg_evb.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * + * Copyright (c) 2021 Nuvoton Technology Corp. + */ + +#include <common.h> +#include <dm.h> +#include <asm/arch/cpu.h> +#include <asm/arch/gcr.h> +#include <asm/io.h> +#include <asm/mach-types.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); + + return 0; +} + +int dram_init(void) +{ + struct npcm_gcr *gcr = (struct npcm_gcr *)npcm_get_base_gcr(); + + int ramsize = (readl(&gcr->intcr3) >> 8) & 0x7; + + switch (ramsize) { + case 0: + gd->ram_size = 0x08000000; /* 128 MB. */ + break; + case 1: + gd->ram_size = 0x10000000; /* 256 MB. */ + break; + case 2: + gd->ram_size = 0x20000000; /* 512 MB. */ + break; + case 3: + gd->ram_size = 0x40000000; /* 1024 MB. */ + break; + case 4: + gd->ram_size = 0x80000000; /* 2048 MB. */ + break; + + default: + break; + } + + return 0; +} diff --git a/include/configs/poleg.h b/include/configs/poleg.h new file mode 100644 index 0000000000..549b198285 --- /dev/null +++ b/include/configs/poleg.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2021 Nuvoton Technology Corp. + */ + +#ifndef __CONFIG_POLEG_H +#define __CONFIG_POLEG_H + +#undef CONFIG_USE_IRQ + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_MACH_TYPE MACH_TYPE_NPCMX50 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 1 +#define CONFIG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/ +#endif +#undef CONFIG_SYS_CACHELINE_SIZE +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_BOOTMAPSZ (0x30 << 20) +#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CONFIG_SYS_INIT_SP_ADDR (0x00008000 - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x08000000) + +#define CONFIG_STANDALONE_LOAD_ADDR 0x10000000 + +#ifndef CONFIG_SYS_MEM_TOP_HIDE +/* 16MB Graphics Memory size to hide + 32MB for VCD ECE DVC. */ +#define CONFIG_SYS_MEM_TOP_HIDE ((16 << 20) + (32 << 20)) +#endif +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 57600, 38400} + +#define CONFIG_SYS_HZ 1000 + +/* Default environemnt variables */ +#define CONFIG_BOOTCOMMAND "run common_bootargs; run romboot" +#define CONFIG_SERVERIP 192.168.0.1 +#define CONFIG_IPADDR 192.168.0.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "ethact=eth${eth_num}\0" \ + "romboot=echo Booting from flash; echo +++ uimage at 0x${uimage_flash_addr}; " \ + "echo Using bootargs: ${bootargs};bootm ${uimage_flash_addr}\0" \ + "autostart=yes\0" \ + "eth_num=0\0" \ + "ethaddr=00:00:F7:A0:00:FC\0" \ + "eth1addr=00:00:F7:A0:00:FD\0" \ + "eth2addr=00:00:F7:A0:00:FE\0" \ + "eth3addr=00:00:F7:A0:00:FF\0" \ + "common_bootargs=setenv bootargs earlycon=${earlycon} root=/dev/ram " \ + "console=${console} mem=${mem} ramdisk_size=48000 basemac=${ethaddr}\0" \ + "sd_prog=fatload mmc 0 10000000 image-bmc; cp.b 10000000 80000000 ${filesize}\0" \ + "sd_run=fatload mmc 0 10000000 image-bmc; bootm 10200000\0" \ + "\0" + +#endif diff --git a/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h b/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h new file mode 100644 index 0000000000..2831918804 --- /dev/null +++ b/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2020 Nuvoton Technology corporation. + +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H +#define _DT_BINDINGS_NPCM8XX_RESET_H + +#define NPCM7XX_RESET_IPSRST1 0x20 +#define NPCM7XX_RESET_IPSRST2 0x24 +#define NPCM7XX_RESET_IPSRST3 0x34 + +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */ +#define NPCM7XX_RESET_SPI3 1 +#define NPCM7XX_RESET_UDC1 5 +#define NPCM7XX_RESET_EMAC1 6 +#define NPCM7XX_RESET_UART_2_3 7 +#define NPCM7XX_RESET_UDC2 8 +#define NPCM7XX_RESET_PECI 9 +#define NPCM7XX_RESET_AES 10 +#define NPCM7XX_RESET_UART_0_1 11 +#define NPCM7XX_RESET_MC 12 +#define NPCM7XX_RESET_SMB2 13 +#define NPCM7XX_RESET_SMB3 14 +#define NPCM7XX_RESET_SMB4 15 +#define NPCM7XX_RESET_SMB5 16 +#define NPCM7XX_RESET_PWM_M0 18 +#define NPCM7XX_RESET_TIMER_0_4 19 +#define NPCM7XX_RESET_TIMER_5_9 20 +#define NPCM7XX_RESET_EMAC2 21 +#define NPCM7XX_RESET_UDC4 22 +#define NPCM7XX_RESET_UDC5 23 +#define NPCM7XX_RESET_UDC6 24 +#define NPCM7XX_RESET_UDC3 25 +#define NPCM7XX_RESET_ADC 27 +#define NPCM7XX_RESET_SMB6 28 +#define NPCM7XX_RESET_SMB7 29 +#define NPCM7XX_RESET_SMB0 30 +#define NPCM7XX_RESET_SMB1 31 + +/* Reset lines on IP2 reset module (NPCM8XX_RESET_IPSRST2) */ +#define NPCM7XX_RESET_MFT0 0 +#define NPCM7XX_RESET_MFT1 1 +#define NPCM7XX_RESET_MFT2 2 +#define NPCM7XX_RESET_MFT3 3 +#define NPCM7XX_RESET_MFT4 4 +#define NPCM7XX_RESET_MFT5 5 +#define NPCM7XX_RESET_MFT6 6 +#define NPCM7XX_RESET_MFT7 7 +#define NPCM7XX_RESET_MMC 8 +#define NPCM7XX_RESET_SDHC 9 +#define NPCM7XX_RESET_GFX_SYS 10 +#define NPCM7XX_RESET_AHB_PCIBRG 11 +#define NPCM7XX_RESET_VDMA 12 +#define NPCM7XX_RESET_ECE 13 +#define NPCM7XX_RESET_VCD 14 +#define NPCM7XX_RESET_OTP 16 +#define NPCM7XX_RESET_SIOX1 18 +#define NPCM7XX_RESET_SIOX2 19 +#define NPCM7XX_RESET_3DES 21 +#define NPCM7XX_RESET_PSPI1 22 +#define NPCM7XX_RESET_PSPI2 23 +#define NPCM7XX_RESET_GMAC2 25 +#define NPCM7XX_RESET_USBH1 26 +#define NPCM7XX_RESET_GMAC1 28 +#define NPCM7XX_RESET_CP1 31 + +/* Reset lines on IP3 reset module (NPCM8XX_RESET_IPSRST3) */ +#define NPCM7XX_RESET_PWM_M1 0 +#define NPCM7XX_RESET_SMB12 1 +#define NPCM7XX_RESET_SPIX 2 +#define NPCM7XX_RESET_SMB13 3 +#define NPCM7XX_RESET_UDC0 4 +#define NPCM7XX_RESET_UDC7 5 +#define NPCM7XX_RESET_UDC8 6 +#define NPCM7XX_RESET_UDC9 7 +#define NPCM7XX_RESET_PCI_MAILBOX 9 +#define NPCM7XX_RESET_SMB14 12 +#define NPCM7XX_RESET_SHA 13 +#define NPCM7XX_RESET_SEC_ECC 14 +#define NPCM7XX_RESET_PCIE_RC 15 +#define NPCM7XX_RESET_TIMER_10_14 16 +#define NPCM7XX_RESET_RNG 17 +#define NPCM7XX_RESET_SMB15 18 +#define NPCM7XX_RESET_SMB8 19 +#define NPCM7XX_RESET_SMB9 20 +#define NPCM7XX_RESET_SMB10 21 +#define NPCM7XX_RESET_SMB11 22 +#define NPCM7XX_RESET_ESPI 23 +#define NPCM7XX_RESET_USBPHY1 24 +#define NPCM7XX_RESET_USBPHY2 25 + +#endif