On Thu, 3 Aug 2023 at 11:44, Jonas Karlman jonas@kwiboo.se wrote:
rk3568_set_drive configures a second reg for specific pins. Mainline linux does not do this and vendor U-Boot only run similar code when bit 14 and 15 are both 0 in PMU_GRF_SOC_CON0. Something that presumably only early revisions of the SoC have, all my RK3566/RK3568 boards read back bit 15 as 1, even on boards dated back to 21H1.
This cause e.g. ethernet PHY on Radxa CM3-IO board not to work after drive is configured according to the device tree.
Input schmitt is configured in 2-bit fields on RK3568 compared to earlier generation and 2'b10 should be used to enable input schmitt.
Remove the code that presumably was intended for early pre-production revisions of the SoC and write correct values for input schmitt setting. Also change to use regmap_update_bits to closer match linux driver.
Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver") Signed-off-by: Jonas Karlman jonas@kwiboo.se
drivers/pinctrl/rockchip/pinctrl-rk3568.c | 52 ++++++----------------- 1 file changed, 14 insertions(+), 38 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org