-----Ursprüngliche Nachricht----- Von: Bin Meng [mailto:bmeng.cn@gmail.com] Gesendet: Donnerstag, 13. Dezember 2018 14:37 An: Stefan Theil Cc: U-Boot Mailing List Betreff: Re: Re: [U-Boot] [PATCH] zynq-gem: Flush cache before handing RX packet to receive handler
Hi Stefan,
On Thu, Dec 13, 2018 at 9:26 PM Stefan Theil <Stefan.Theil@mixed- mode.de> wrote:
Hmm good question. I went with flush because that's what's done in the
transmit function:
addr = (ulong) ptr; addr &= ~(ARCH_DMA_MINALIGN - 1); size = roundup(len, ARCH_DMA_MINALIGN); flush_dcache_range(addr,
addr
- size);
addr = (ulong)priv->rxbuffers; addr &= ~(ARCH_DMA_MINALIGN - 1); size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); flush_dcache_range(addr, addr + size); barrier();
But since we actually want the uncached data invalidation seems logical. I
have to admit though, I don't have much experience with caches. This patch completely fixed my problem... Maybe somebody with a bit more expertise can add their opinion?
It should be 'invalidate' primitive when it comes to the RX path. For TX path, it should be 'flush'.
Regards, Bin
Then why are all receive buffers flushed before sending a packet? In any case, I'll try it with invalidate and submit an updated version.
Regards, Stefan