According to the PL310 TRM, 0 in the latency fields(setup/read/write) indicates 1 cycle of latency for Tag and Data RAM latency control registers. If we want to set 1 cycle of latency, we need to clear the field actually. The TRM is as below: https://developer.arm.com/documentation/ddi0246/h/programmers-model/register...
Signed-off-by: Haifeng Li haifeng.li@timesintelli.com --- drivers/cache/cache-l2x0.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c index a1556fbf17..16b583ddd2 100644 --- a/drivers/cache/cache-l2x0.c +++ b/drivers/cache/cache-l2x0.c @@ -38,19 +38,27 @@ static void l2c310_of_parse_and_init(struct udevice *dev)
writel(saved_reg, ®s->pl310_aux_ctrl);
- saved_reg = readl(®s->pl310_tag_latency_ctrl); - if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3)) + if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3)) { + saved_reg = readl(®s->pl310_tag_latency_ctrl); + clrbits_le32(&saved_reg, L310_LATENCY_CTRL_WR(7) | + L310_LATENCY_CTRL_RD(7) | + L310_LATENCY_CTRL_SETUP(7)); saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) | L310_LATENCY_CTRL_WR(tag[1] - 1) | L310_LATENCY_CTRL_SETUP(tag[2] - 1); - writel(saved_reg, ®s->pl310_tag_latency_ctrl); + writel(saved_reg, ®s->pl310_tag_latency_ctrl); + }
- saved_reg = readl(®s->pl310_data_latency_ctrl); - if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3)) + if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3)) { + saved_reg = readl(®s->pl310_data_latency_ctrl); + clrbits_le32(&saved_reg, L310_LATENCY_CTRL_WR(7) | + L310_LATENCY_CTRL_RD(7) | + L310_LATENCY_CTRL_SETUP(7)); saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) | L310_LATENCY_CTRL_WR(tag[1] - 1) | L310_LATENCY_CTRL_SETUP(tag[2] - 1); - writel(saved_reg, ®s->pl310_data_latency_ctrl); + writel(saved_reg, ®s->pl310_data_latency_ctrl); + }
/* Enable the L2 cache */ setbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);