Hello Hans,
On Mon, 19 Jan 2015 20:04:58 +0100, Hans de Goede hdegoede@redhat.com wrote:
Hi,
On 17-01-15 23:51, Ian Campbell wrote:
On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
According to the "Cortex-A7 MPCore Technical Reference Manual":
"You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed."
Given that this is a feature of the Cortex-A7 (actually, I believe it applies to at least Cortex-A15 too) and not really specific to sunxi, perhaps we can make this more generic?
Strange enough the bit is different between the A7 and A15, for the A7 the docs say it must be set before doing anything with caches, on the A15 it only needs to be set for the core to accept cache management operations from other cpu cores (or so the docs say), which is likely why it is not in the standard init sequence yet, as for u-boot it seems to only be necessary to do this on a Cortex A7. I agree that it would be good to move this to the generic start.S though, Albert ?
[...]
Since arch/arm/cpu/armv7/start.S: cpu_init_cp15 does several cache operations, we should thus enable the SMP bit earlier, and the only chance to do that is to do it at save_boot_params time.
Would it be so terrible to add an ifdef CORTEX_A7 here, or to call out to (or call as a macro) a soc_init_cp15?
From my pov no that would not be too terrible, but ...
I'm cc-ing Albert for input these questions.
That indeed is Albert's call.
Will look into this today.
Amicalement,