Dear Haiying.Wang@freescale.com,
In message 1296499317-26616-7-git-send-email-Haiying.Wang@freescale.com you wrote:
From: Haiying Wang Haiying.Wang@freescale.com
P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal.
P1021MDS has to load the microcode from NAND flash, this patch defines misc_init_r() for loading ucode and initializing qe.
...
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 282ab23..04d7987 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c
...
+#ifdef CONFIG_P1021 +#define BCSR11_ENET_MICRST 0x20 +#endif
/* Default UTBIPAR SMI address */ #ifndef CONFIG_UTBIPAR_INIT_TBIPA @@ -588,9 +591,25 @@ static void phy_change(struct eth_device *dev) { uec_private_t *uec = (uec_private_t *)dev->priv;
+#ifdef CONFIG_P1021
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- /* QE9 and QE12 need to be set for enabling QE MII managment signals */
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
...
Can we please avoid having board specific code in common files?
If this is really necessary, it shoud be a feature-specific #define, not a board specific one.
@@ -425,6 +469,8 @@ #define CONFIG_PCI_PNP /* do pci plug-and-play */ #endif
+#define CONFIG_E1000
In which way is this change related to this commit?
Best regards,
Wolfgang Denk