Hi Bo,
I think you should check more detail in section 12 "Standard Boot Strategies". It needs more things to do. I will give a picture in following answer.
<snip>
As the code execute on NOR flash, so, the SPL configure the CPU clock will cause SMC access abortion. So, a brief guide as following:
The datasheet says the user software in external memory should:
a) Enable the 32768 Hz oscillator if best accuracy is needed. b) Reprogram the SMC setup, cycle, hold, mode timing registers for EBI CS0, to adapt them to the new clock. c) Program the PMC (Main Oscillator Enable or Bypass mode). d) Program and start the PLL. e) Switch the system clock to the new value.
So my current thinking is that:
- I am not so worried about (a), as I don't think accuracy is essential at this point in time. - (b) needs to be taken care of in the steps that you outline below. - (c) ??? - The function at91_pmc_init() in board\atmel\sama5d3xek\sama5d3xek.c takes care of items (d) and (e)
It has been a while since I have done this much low level code so I may be a little rusty :-)
- Write a ram function, which do as the datasheet says.
- Add copy function (copy the ram function into sram) at the begin of
the SPL code. 3. After the step 1, finished to execute, then, you can jump back to NOR to execute.
I'm not sure I follow how to do this. Are there any similar implementations elsewhere in U-Boot that I could use as a reference. I should say that ARM assembler isn't my strongest skill as most of my previous experience has been gained with x86 and MIPS.
Thanks for all your help.
Andy.