Add support for Veloce - zynqmp emulation platform. Platform doesn't support SDHCI.
Signed-off-by: Michal Simek michal.simek@xilinx.com ---
arch/arm/cpu/armv8/zynqmp/clk.c | 3 +++ arch/arm/cpu/armv8/zynqmp/cpu.c | 2 ++ arch/arm/include/asm/arch-zynqmp/hardware.h | 1 + board/xilinx/zynqmp/zynqmp.c | 8 ++++++-- 4 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c index 0af619d92fde..9147fa749507 100644 --- a/arch/arm/cpu/armv8/zynqmp/clk.c +++ b/arch/arm/cpu/armv8/zynqmp/clk.c @@ -6,6 +6,7 @@ */
#include <common.h> +#include <asm/arch/clk.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h>
@@ -16,6 +17,8 @@ unsigned long get_uart_clk(int dev_id) u32 ver = zynqmp_get_silicon_version();
switch (ver) { + case ZYNQMP_CSU_VERSION_VELOCE: + return 96000; case ZYNQMP_CSU_VERSION_EP108: return 25000000; } diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 11958fea6f11..60d7d20e17c8 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -20,6 +20,8 @@ unsigned int zynqmp_get_silicon_version(void) gd->cpu_clk = get_tbclk();
switch (gd->cpu_clk) { + case 0 ... 1000000: + return ZYNQMP_CSU_VERSION_VELOCE; case 50000000: return ZYNQMP_CSU_VERSION_QEMU; } diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 3df3147fc4c3..188b5c2144af 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -84,6 +84,7 @@ struct apu_regs { /* Board version value */ #define ZYNQMP_CSU_VERSION_SILICON 0x0 #define ZYNQMP_CSU_VERSION_EP108 0x1 +#define ZYNQMP_CSU_VERSION_VELOCE 0x2 #define ZYNQMP_CSU_VERSION_QEMU 0x3
#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 1325bca5e552..e38948426d70 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -56,14 +56,18 @@ int board_mmc_init(bd_t *bd) { int ret = 0;
+ u32 ver = zynqmp_get_silicon_version(); + + if (ver != ZYNQMP_CSU_VERSION_VELOCE) { #if defined(CONFIG_ZYNQ_SDHCI) # if defined(CONFIG_ZYNQ_SDHCI0) - ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); + ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); # endif # if defined(CONFIG_ZYNQ_SDHCI1) - ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); + ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); # endif #endif + }
return ret; }