Hello,
On 10/28/2014 02:10 AM, Simon Glass wrote:
Hi,
On 24 October 2014 09:44, Przemyslaw Marczak p.marczak@samsung.com wrote:
This patch adds extra gpio part addresses to exynos4/4x12_gpio_data arrays, which are required since the gpio enum lists are linear
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
arch/arm/include/asm/arch-exynos/gpio.h | 59 ++++++++++++++++++++++----------- 1 file changed, 39 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index ad2ece6..02287de 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -284,7 +284,10 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_Y65, EXYNOS4_GPIO_Y66, EXYNOS4_GPIO_Y67,
EXYNOS4_GPIO_X00, /* 256 0x100 */
/* GPIO_PART2_1 STARTS */EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0, EXYNOS4_GPIO_X01, EXYNOS4_GPIO_X02, EXYNOS4_GPIO_X03,@@ -318,8 +321,8 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_X37,
/* GPIO_PART3_STARTS */
EXYNOS4_GPIO_MAX_PORT_PART_2, /* 288 0x120 */EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2,
EXYNOS4_GPIO_MAX_PORT_PART_2_1, /* 288 0x120 */EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1, EXYNOS4_GPIO_Z1, EXYNOS4_GPIO_Z2, EXYNOS4_GPIO_Z3,@@ -332,7 +335,7 @@ enum exynos4_gpio_pin { };
enum exynos4X12_gpio_pin {
/* GPIO_PART1_STARTS */
/* EXYNOS4X12_GPIO_PART1_0 starts here */ EXYNOS4X12_GPIO_A00, /* 0 */ EXYNOS4X12_GPIO_A01, EXYNOS4X12_GPIO_A02,@@ -389,7 +392,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_D15, EXYNOS4X12_GPIO_D16, EXYNOS4X12_GPIO_D17,
EXYNOS4X12_GPIO_F00, /* 56 0x38 */
EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 *//* EXYNOS4X12_GPIO_PART1_1 starts here */EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, EXYNOS4X12_GPIO_F01, EXYNOS4X12_GPIO_F02, EXYNOS4X12_GPIO_F03,@@ -421,7 +426,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_F35, EXYNOS4X12_GPIO_F36, EXYNOS4X12_GPIO_F37,
EXYNOS4X12_GPIO_J00, /* 88 0x58 */
EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 *//* EXYNOS4X12_GPIO_PART1_2 starts here */EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, EXYNOS4X12_GPIO_J01, EXYNOS4X12_GPIO_J02, EXYNOS4X12_GPIO_J03,@@ -438,9 +445,12 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_J16, EXYNOS4X12_GPIO_J17,
/* GPIO_PART2_STARTS */EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1,
/*** EXYNOS4X12_GPIO_PART2_0 is not used* EXYNOS4X12_GPIO_PART2_1 starts here*/EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, EXYNOS4X12_GPIO_K01, EXYNOS4X12_GPIO_K02, EXYNOS4X12_GPIO_K03,@@ -552,7 +562,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y65, EXYNOS4X12_GPIO_Y66, EXYNOS4X12_GPIO_Y67,
EXYNOS4X12_GPIO_M00, /* 216 0xd8 */
EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 *//* EXYNOS4X12_GPIO_PART2_2 starts here */EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, EXYNOS4X12_GPIO_M01, EXYNOS4X12_GPIO_M02, EXYNOS4X12_GPIO_M03,@@ -592,7 +604,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_M45, EXYNOS4X12_GPIO_M46, EXYNOS4X12_GPIO_M47,
EXYNOS4X12_GPIO_X00, /* 256 0x100 */
EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 *//* EXYNOS4X12_GPIO_PART2_3 starts here */EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, EXYNOS4X12_GPIO_X01, EXYNOS4X12_GPIO_X02, EXYNOS4X12_GPIO_X03,@@ -625,9 +639,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_X36, EXYNOS4X12_GPIO_X37,
/* GPIO_PART3_STARTS */EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2,
/* EXYNOS4X12_GPIO_PART3 starts here */EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, EXYNOS4X12_GPIO_Z1, EXYNOS4X12_GPIO_Z2, EXYNOS4X12_GPIO_Z3,@@ -636,7 +650,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Z6, EXYNOS4X12_GPIO_Z7,
/* GPIO_PART4_STARTS */
/* EXYNOS4X12_GPIO_PART4 starts here */ EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */ EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3, EXYNOS4X12_GPIO_V01,@@ -1339,17 +1353,22 @@ struct gpio_info { unsigned int max_gpio; /* Maximum GPIO in this part */ };
-#define EXYNOS4_GPIO_NUM_PARTS 3 +#define EXYNOS4_GPIO_NUM_PARTS 4 static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = { { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
{ EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 },
{ EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 },{ EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 }, { EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT },-#define EXYNOS4X12_GPIO_NUM_PARTS 4 +#define EXYNOS4X12_GPIO_NUM_PARTS 8 static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = {
{ EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 },{ EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 },
{ EXYNOS4X12_GPIO_PART1_0, EXYNOS4X12_GPIO_MAX_PORT_PART_1_0 },{ EXYNOS4X12_GPIO_PART1_1, EXYNOS4X12_GPIO_MAX_PORT_PART_1_1 },{ EXYNOS4X12_GPIO_PART1_2, EXYNOS4X12_GPIO_MAX_PORT_PART_1_2 },{ EXYNOS4X12_GPIO_PART2_1, EXYNOS4X12_GPIO_MAX_PORT_PART_2_1 },{ EXYNOS4X12_GPIO_PART2_2, EXYNOS4X12_GPIO_MAX_PORT_PART_2_2 },{ EXYNOS4X12_GPIO_PART2_3, EXYNOS4X12_GPIO_MAX_PORT_PART_2_3 },Again I wonder if we can just number these 0 to 7?
And again, if we want to remove this interface in the future, the old EXYNOS4X12_GPIO_PART[x]_BASE will be still unchanged an can be used as it is.
{ EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 }, { EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT },};
1.9.1
Regards, Simon
Best regards,