Looking over Freescale's Manuals for a few different CPUs (8572, 8641, 8548, P2020, P4080, 8349) I'm see very different definitions of the CAPTURE_ECC register. I assume these parts all share the same intellectual property, so had expected the CAPTURE_ECC definition to be similar between parts. Some of the definitions don't make sense and I was hoping someone had some insight.
The 8641 and P8040 both state: 16:23—8-bit ECC code for 1st 32 bits 24:31—8-bit ECC code for 2nd 32 bits Note: In 64-bit mode, only 24:31 should be used, although 16:23 shows the 8-bit ECC code replicated.
The 8572 and 2020 both state: 0:7—8-bit ECC for first 16 bits in 16-bit bus mode; should be ignored for 32-bit and 64-bit mode 8:15—8-bit ECC for second 16 bits in 16-bit bus mode; 1st 32 bits in 32-bit bus mode; should be ignored for 64-bit bus mode 16:23—8-bit ECC for third 16 bits in 16-bit bus mode; should be ignored for 32-bit and 64-bit mode 24:31—8-bit ECC for fourth 16 bits in 16-bit bus mode; 2nd 32 bits in 32-bit bus mode; all 64-bits in 64-bit bus mode
The 8548 and 8349 both just use 8-bits of the register and state: Error capture ECC. Captures the ECC bits on the data path whenever errors are detected.
I only have boards with a 64-bit bus, and reading the value of the CAPTURE_ECC register always returns the same byte repeated 4 times, eg 0xabababab.
I was tweaking some ECC code and am having problems doing it the "right way" to support 32-bit wide buses. Anyone have additional info? Does the CAPTURE_ECC register only hold 8-bits of data? 16-bits of data with a 32-bit bus? 32-bits of data? Are the definitions of the register really different between processors?
Thanks for any help, Peter