From: Thierry Reding treding@nvidia.com
size is always non-negative, so it should be unsigned, whereas the address and size can be larger than 32 bit on 64-bit architectures. Change the mmu_set_region_dcache_behaviour() to use these types in anticipation of making the API available on other architectures.
Signed-off-by: Thierry Reding treding@nvidia.com --- arch/arm/include/asm/system.h | 2 +- arch/arm/lib/cache-cp15.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index d51ba668f323..4b771c261a8b 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -200,7 +200,7 @@ enum { * \param size size of memory region to change * \param option dcache option to select */ -void mmu_set_region_dcache_behaviour(u32 start, int size, +void mmu_set_region_dcache_behaviour(unsigned long start, unsigned long size, enum dcache_option option);
/** diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 5fdfdbfca541..b52576dc64bd 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -47,15 +47,15 @@ __weak void mmu_page_table_flush(unsigned long start, unsigned long stop) debug("%s: Warning: not implemented\n", __func__); }
-void mmu_set_region_dcache_behaviour(u32 start, int size, +void mmu_set_region_dcache_behaviour(unsigned long start, unsigned long size, enum dcache_option option) { u32 *page_table = (u32 *)gd->arch.tlb_addr; - u32 upto, end; + unsigned long upto, end;
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; start = start >> MMU_SECTION_SHIFT; - debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size, + debug("%s: start=%lx, size=%lx, option=%d\n", __func__, start, size, option); for (upto = start; upto < end; upto++) set_section_dcache(upto, option);