Hi Simon,
On Thursday 16 November 2017 03:39 PM, Goldschmidt Simon wrote: [...]
This 32-bit spi transfer mode does not seem to be used too often, all other drivers I looked at are transferring byte by byte and thus can not be used as an example.
Additionally, the TI platform Vignesh used obviously does not support unaligned access (which is why he added using bouncebuf here although no dma is used) while mach-socfpga supports unaligned accesses by default.
Its not actually unaligned access, cadence QSPI IP on TI platforms do not support non-byte accesses except for the last word. As per the TRM: "The external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer"
So given my explanation above, what's the preferred way to fix this?
Sorry, I overlooked the fact that bounce_buffer_stop() is calling invalidate_dcache_range(). Somehow, this did not show problems on my platform although its a writeback cache.
I would suggest to revert commit b63b46313 ("spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"). I have seen that non 32 bit accesses cause problems only while writing to flash but not during read operations although the TRM states that both reads and writes are affected. But, since reverting b63b46313 as such does not break TI platforms, I would prefer sending a revert. Meanwhile, I will work on a better patch later.
I thought a framework solution would be better, which is why I modified bouncebuf to work with this, but as cadence_qspi is the only driver using bouncebuf in this fashion for now, I'm open for suggestions.
Lets not touch bouncebuf for now.
I need this driver fixed, so whatever way will be accepted is fine by me, I guess. Just let me know.
Sorry for the trouble. I am okay with reverting the patch affecting read path.