Hi Markus,
good work. I gave it a try on our PLU405 board (405EP) with a PCI attached OHCI controller (ISP1561). I had to add a offset to the dma'ed addresses, so that the USB controller can access the correct locations in RAM.
CONFIG_PCI_CONFIG_HOST_BRIDGE must be defined and the pciconfighost variable must be set. After this, RAM is accessible at PCI address 0x8000000. I modified drivers/usb_ohci.c to support this offset (CFG_USB_OHCI_DMA_BASE).
I am not sure if there is a better way to get PCI OHCI working with a 405 CPU. U-Boot does not setup the PLB/PCI bridge so that the RAM is accessible at PCI address 0.
Here is my patch for discussion:
diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c index 3cef576..943e37d 100644 --- a/drivers/usb_ohci.c +++ b/drivers/usb_ohci.c @@ -81,7 +81,7 @@ * e.g. PCI controllers need this */ #ifdef CFG_OHCI_SWAP_REG_ACCESS -# define readl(a) __swap_16(*((vu_long *)(a))) +# define readl(a) __swap_32(*((vu_long *)(a))) # define writel(a, b) (*((vu_long *)(b)) = __swap_32((vu_long)a)) #else # define readl(a) (*((vu_long *)(a))) @@ -93,9 +93,13 @@ #ifdef CONFIG_PCI_OHCI static struct pci_device_id ohci_pci_ids[] = { {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ + {0x1131, 0x1561}, /* ISP1561 PCI OHCI module ids */ /* Please add supported PCI OHCI controller ids here */ {0, 0} }; +#ifndef CFG_USB_OHCI_DMA_BASE +# define CFG_USB_OHCI_DMA_BASE 0 +#endif #endif
#ifdef DEBUG @@ -631,7 +635,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi) case PIPE_CONTROL: ed->hwNextED = 0; if (ohci->ed_controltail == NULL) { - writel (ed, &ohci->regs->ed_controlhead); + writel (CFG_USB_OHCI_DMA_BASE + (u32)ed, &ohci->regs->ed_controlhead); } else { ohci->ed_controltail->hwNextED = m32_swap ((unsigned long)ed); } @@ -647,7 +651,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi) case PIPE_BULK: ed->hwNextED = 0; if (ohci->ed_bulktail == NULL) { - writel (ed, &ohci->regs->ed_bulkhead); + writel (CFG_USB_OHCI_DMA_BASE + (u32)ed, &ohci->regs->ed_bulkhead); } else { ohci->ed_bulktail->hwNextED = m32_swap ((unsigned long)ed); } @@ -721,7 +725,7 @@ static int ep_unlink (ohci_t *ohci, ed_t *edi) ohci->hc_control &= ~OHCI_CTRL_CLE; writel (ohci->hc_control, &ohci->regs->control); } - writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); + writel (CFG_USB_OHCI_DMA_BASE + m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); } else { ed->ed_prev->hwNextED = ed->hwNextED; } @@ -738,7 +742,7 @@ static int ep_unlink (ohci_t *ohci, ed_t *edi) ohci->hc_control &= ~OHCI_CTRL_BLE; writel (ohci->hc_control, &ohci->regs->control); } - writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); + writel (CFG_USB_OHCI_DMA_BASE + m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); } else { ed->ed_prev->hwNextED = ed->hwNextED; } @@ -790,7 +794,7 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe, ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */ /* dummy td; end of td list for ed */ td = td_alloc (usb_dev); - ed->hwTailP = m32_swap ((unsigned long)td); + ed->hwTailP = m32_swap (CFG_USB_OHCI_DMA_BASE + (unsigned long)td); ed->hwHeadP = ed->hwTailP; ed->state = ED_UNLINK; ed->type = usb_pipetype (pipe); @@ -836,7 +840,7 @@ static void td_fill (ohci_t *ohci, unsigned int info, td_pt->hwNextTD = 0;
/* fill the old dummy TD */ - td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf); + td = urb_priv->td [index] = (td_t *)((m32_swap (urb_priv->ed->hwTailP)-CFG_USB_OHCI_DMA_BASE) & ~0xf);
td->ed = urb_priv->ed; td->next_dl_td = NULL; @@ -853,12 +857,16 @@ static void td_fill (ohci_t *ohci, unsigned int info, data = 0;
td->hwINFO = m32_swap (info); - td->hwCBP = m32_swap ((unsigned long)data); + if (len) { + td->hwCBP = m32_swap (CFG_USB_OHCI_DMA_BASE + (unsigned long)data); + } else { + td->hwCBP = 0; + } if (data) - td->hwBE = m32_swap ((unsigned long)(data + len - 1)); + td->hwBE = m32_swap (CFG_USB_OHCI_DMA_BASE + (unsigned long)(data + len - 1)); else td->hwBE = 0; - td->hwNextTD = m32_swap ((unsigned long)td_pt); + td->hwNextTD = m32_swap (CFG_USB_OHCI_DMA_BASE + (unsigned long)td_pt);
/* append to queue */ td->ed->hwTailP = td->hwNextTD; @@ -949,7 +957,11 @@ static void dl_transfer_length(td_t * td)
tdINFO = m32_swap (td->hwINFO); tdBE = m32_swap (td->hwBE); + if (tdBE) + tdBE -= CFG_USB_OHCI_DMA_BASE; tdCBP = m32_swap (td->hwCBP); + if (tdCBP) + tdCBP -= CFG_USB_OHCI_DMA_BASE;
if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && @@ -975,10 +987,10 @@ static td_t * dl_reverse_done_list (ohci_t *ohci) td_t *td_list = NULL; urb_priv_t *lurb_priv = NULL;
- td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0; + td_list_hc = (m32_swap(ohci->hcca->done_head) - CFG_USB_OHCI_DMA_BASE) & 0xfffffff0; ohci->hcca->done_head = 0;
- while (td_list_hc) { + while (td_list_hc && (td_list_hc != CFG_USB_OHCI_DMA_BASE)) { td_list = (td_t *)td_list_hc;
if (TD_CC_GET (m32_swap (td_list->hwINFO))) { @@ -1001,7 +1013,7 @@ static td_t * dl_reverse_done_list (ohci_t *ohci)
td_list->next_dl_td = td_rev; td_rev = td_list; - td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0; + td_list_hc = (m32_swap (td_list->hwNextTD) - CFG_USB_OHCI_DMA_BASE) & 0xfffffff0; } return td_list; } @@ -1646,7 +1658,8 @@ static int hc_start (ohci_t * ohci) writel (0, &ohci->regs->ed_controlhead); writel (0, &ohci->regs->ed_bulkhead);
- writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ + /* a reset clears this */ + writel (CFG_USB_OHCI_DMA_BASE + (__u32)ohci->hcca, &ohci->regs->hcca);
fminterval = 0x2edf; writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index d02c39b..e309369 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -65,6 +65,7 @@ CFG_CMD_DHCP | \ CFG_CMD_PCI | \ CFG_CMD_IRQ | \ + CFG_CMD_USB | \ CFG_CMD_IDE | \ CFG_CMD_FAT | \ CFG_CMD_ELF | \ @@ -450,4 +451,13 @@ #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 #endif
+#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_PCI_OHCI 1 +#define CFG_OHCI_SWAP_REG_ACCESS 1 +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 +#define CFG_USB_OHCI_SLOT_NAME "ohci_pci" +#define CONFIG_USB_STORAGE 1 +/* RAM is seen at 0x8000000 from the PCI bus */ +#define CFG_USB_OHCI_DMA_BASE 0x80000000 + #endif /* __CONFIG_H */
Regards Matthias