2.2.5.2 of Marvell PXA27x Processor Family Developers Manual says: "The PXA27x processor cache configuration is identical to that of the PXA255 processor."
As a result, it is perfectly legitimate to use PXA25X 'lock_cache_for_stack' on PXA27X as well.
Signed-off-by: Sergey Yanovich ynvich@gmail.com --- arch/arm/cpu/pxa/start.S | 10 ++++++++-- include/configs/lp8x4x.h | 5 +++-- 2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index ada91a6..5ea512e 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -40,6 +40,12 @@ #include <version.h>
#ifdef CONFIG_CPU_PXA25X +#ifndef CONFIG_PXA2XX_CACHE_AS_RAM +#define CONFIG_PXA2XX_CACHE_AS_RAM +#endif +#endif + +#ifdef CONFIG_PXA2XX_CACHE_AS_RAM #if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) #error "Init SP address must be set to 0xfffff800 for PXA250" #endif @@ -164,7 +170,7 @@ reset: bl cpu_init_crit #endif
-#ifdef CONFIG_CPU_PXA25X +#ifdef CONFIG_PXA2XX_CACHE_AS_RAM bl lock_cache_for_stack #endif
@@ -482,7 +488,7 @@ fiq: * This is useful on PXA25x and PXA26x in early bootstages, where there is no * other possible memory available to hold stack. */ -#ifdef CONFIG_CPU_PXA25X +#ifdef CONFIG_PXA2XX_CACHE_AS_RAM .macro CPWAIT reg mrc p15, 0, \reg, c2, c0, 0 mov \reg, \reg diff --git a/include/configs/lp8x4x.h b/include/configs/lp8x4x.h index 026f321..27ff2f4 100644 --- a/include/configs/lp8x4x.h +++ b/include/configs/lp8x4x.h @@ -149,8 +149,9 @@
#define CONFIG_SYS_LOAD_ADDR 0xa0008000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Use first 64kb bank of the internal SRAM */ -#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 +/* Use CPU data cache as internal RAM */ +#define CONFIG_PXA2XX_CACHE_AS_RAM +#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
/* * NOR FLASH