Hi Marek,
I'm currently working on U-Boot support for the Freescale i.mx28evk board. It started out as an update of the old Freescale supplied U-Boot 2009.08, but it ended up in reconfiguring your work on the Denx m28evk module. Today I stumbled upon a problem with Ethernet.
It turned out that communication with the PHYs didn't work, because the SoC isn't supplying ENET_CLK. The Ethernet clock is configured properly by cpu_eth_init in ./arch/arm/cpu/arm926ejs/mx28/mx28.c. But later in the boot process, board_eth_init in board/denx/m28evk/m28evk.c tries to configure the Ethernet clock again. Unfortunately that second configuration is just disabling the clock: clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, CLKCTRL_ENET_TIME_SEL_RMII_CLK); After removing this line, I measured a 25MHz clock, communication with the PHYs worked and I successfully tftp'ed a kernel from my server.
Does Ethernet on your board work? Does you board have an external clock oscillator for the PHYs? If not, do you agree with removing this line?
Cheers,
Robert.