Signed-off-by: Cédric Le Goater clg@kaod.org Reviewed-by: Joel Stanley joel@jms.id.au Acked-by: Joe Hershberger joe.hershberger@ni.com --- drivers/net/ftgmac100.h | 154 ++++++++++++++++++++-------------------- 1 file changed, 77 insertions(+), 77 deletions(-)
diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h index ffbe1f3e3fa7..439b14d71e4b 100644 --- a/drivers/net/ftgmac100.h +++ b/drivers/net/ftgmac100.h @@ -70,48 +70,48 @@ struct ftgmac100 { /* * Interrupt status register & interrupt enable register */ -#define FTGMAC100_INT_RPKT_BUF (1 << 0) -#define FTGMAC100_INT_RPKT_FIFO (1 << 1) -#define FTGMAC100_INT_NO_RXBUF (1 << 2) -#define FTGMAC100_INT_RPKT_LOST (1 << 3) -#define FTGMAC100_INT_XPKT_ETH (1 << 4) -#define FTGMAC100_INT_XPKT_FIFO (1 << 5) -#define FTGMAC100_INT_NO_NPTXBUF (1 << 6) -#define FTGMAC100_INT_XPKT_LOST (1 << 7) -#define FTGMAC100_INT_AHB_ERR (1 << 8) -#define FTGMAC100_INT_PHYSTS_CHG (1 << 9) -#define FTGMAC100_INT_NO_HPTXBUF (1 << 10) +#define FTGMAC100_INT_RPKT_BUF BIT(0) +#define FTGMAC100_INT_RPKT_FIFO BIT(1) +#define FTGMAC100_INT_NO_RXBUF BIT(2) +#define FTGMAC100_INT_RPKT_LOST BIT(3) +#define FTGMAC100_INT_XPKT_ETH BIT(4) +#define FTGMAC100_INT_XPKT_FIFO BIT(5) +#define FTGMAC100_INT_NO_NPTXBUF BIT(6) +#define FTGMAC100_INT_XPKT_LOST BIT(7) +#define FTGMAC100_INT_AHB_ERR BIT(8) +#define FTGMAC100_INT_PHYSTS_CHG BIT(9) +#define FTGMAC100_INT_NO_HPTXBUF BIT(10)
/* * Interrupt timer control register */ #define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) #define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) -#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7) +#define FTGMAC100_ITC_RXINT_TIME_SEL BIT(7) #define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) #define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) -#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15) +#define FTGMAC100_ITC_TXINT_TIME_SEL BIT(15)
/* * Automatic polling timer control register */ #define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) -#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) +#define FTGMAC100_APTC_RXPOLL_TIME_SEL BIT(4) #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) -#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) +#define FTGMAC100_APTC_TXPOLL_TIME_SEL BIT(12)
/* * DMA burst length and arbitration control register */ #define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0) #define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3) -#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6) +#define FTGMAC100_DBLAC_RX_THR_EN BIT(6) #define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8) #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) #define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) #define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) -#define FTGMAC100_DBLAC_IFG_INC (1 << 23) +#define FTGMAC100_DBLAC_IFG_INC BIT(23)
/* * DMA FIFO status register @@ -122,12 +122,12 @@ struct ftgmac100 { #define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf) #define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3) #define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf) -#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26) -#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27) -#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28) -#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29) -#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30) -#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31) +#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY BIT(26) +#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY BIT(27) +#define FTGMAC100_DMAFIFOS_RXDMA_GRANT BIT(28) +#define FTGMAC100_DMAFIFOS_TXDMA_GRANT BIT(29) +#define FTGMAC100_DMAFIFOS_RXDMA_REQ BIT(30) +#define FTGMAC100_DMAFIFOS_TXDMA_REQ BIT(31)
/* * Receive buffer size register @@ -137,26 +137,26 @@ struct ftgmac100 { /* * MAC control register */ -#define FTGMAC100_MACCR_TXDMA_EN (1 << 0) -#define FTGMAC100_MACCR_RXDMA_EN (1 << 1) -#define FTGMAC100_MACCR_TXMAC_EN (1 << 2) -#define FTGMAC100_MACCR_RXMAC_EN (1 << 3) -#define FTGMAC100_MACCR_RM_VLAN (1 << 4) -#define FTGMAC100_MACCR_HPTXR_EN (1 << 5) -#define FTGMAC100_MACCR_LOOP_EN (1 << 6) -#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7) -#define FTGMAC100_MACCR_FULLDUP (1 << 8) -#define FTGMAC100_MACCR_GIGA_MODE (1 << 9) -#define FTGMAC100_MACCR_CRC_APD (1 << 10) -#define FTGMAC100_MACCR_RX_RUNT (1 << 12) -#define FTGMAC100_MACCR_JUMBO_LF (1 << 13) -#define FTGMAC100_MACCR_RX_ALL (1 << 14) -#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15) -#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16) -#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17) -#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18) -#define FTGMAC100_MACCR_FAST_MODE (1 << 19) -#define FTGMAC100_MACCR_SW_RST (1 << 31) +#define FTGMAC100_MACCR_TXDMA_EN BIT(0) +#define FTGMAC100_MACCR_RXDMA_EN BIT(1) +#define FTGMAC100_MACCR_TXMAC_EN BIT(2) +#define FTGMAC100_MACCR_RXMAC_EN BIT(3) +#define FTGMAC100_MACCR_RM_VLAN BIT(4) +#define FTGMAC100_MACCR_HPTXR_EN BIT(5) +#define FTGMAC100_MACCR_LOOP_EN BIT(6) +#define FTGMAC100_MACCR_ENRX_IN_HALFTX BIT(7) +#define FTGMAC100_MACCR_FULLDUP BIT(8) +#define FTGMAC100_MACCR_GIGA_MODE BIT(9) +#define FTGMAC100_MACCR_CRC_APD BIT(10) +#define FTGMAC100_MACCR_RX_RUNT BIT(12) +#define FTGMAC100_MACCR_JUMBO_LF BIT(13) +#define FTGMAC100_MACCR_RX_ALL BIT(14) +#define FTGMAC100_MACCR_HT_MULTI_EN BIT(15) +#define FTGMAC100_MACCR_RX_MULTIPKT BIT(16) +#define FTGMAC100_MACCR_RX_BROADPKT BIT(17) +#define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18) +#define FTGMAC100_MACCR_FAST_MODE BIT(19) +#define FTGMAC100_MACCR_SW_RST BIT(31)
/* * PHY control register @@ -165,8 +165,8 @@ struct ftgmac100 { #define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f) #define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) #define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) -#define FTGMAC100_PHYCR_MIIRD (1 << 26) -#define FTGMAC100_PHYCR_MIIWR (1 << 27) +#define FTGMAC100_PHYCR_MIIRD BIT(26) +#define FTGMAC100_PHYCR_MIIWR BIT(27)
/* * PHY data register @@ -185,20 +185,20 @@ struct ftgmac100_txdes { } __attribute__ ((aligned(16)));
#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) -#define FTGMAC100_TXDES0_EDOTR (1 << 15) -#define FTGMAC100_TXDES0_CRC_ERR (1 << 19) -#define FTGMAC100_TXDES0_LTS (1 << 28) -#define FTGMAC100_TXDES0_FTS (1 << 29) -#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31) +#define FTGMAC100_TXDES0_EDOTR BIT(15) +#define FTGMAC100_TXDES0_CRC_ERR BIT(19) +#define FTGMAC100_TXDES0_LTS BIT(28) +#define FTGMAC100_TXDES0_FTS BIT(29) +#define FTGMAC100_TXDES0_TXDMA_OWN BIT(31)
#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) -#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16) -#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17) -#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18) -#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19) -#define FTGMAC100_TXDES1_LLC (1 << 22) -#define FTGMAC100_TXDES1_TX2FIC (1 << 30) -#define FTGMAC100_TXDES1_TXIC (1 << 31) +#define FTGMAC100_TXDES1_INS_VLANTAG BIT(16) +#define FTGMAC100_TXDES1_TCP_CHKSUM BIT(17) +#define FTGMAC100_TXDES1_UDP_CHKSUM BIT(18) +#define FTGMAC100_TXDES1_IP_CHKSUM BIT(19) +#define FTGMAC100_TXDES1_LLC BIT(22) +#define FTGMAC100_TXDES1_TX2FIC BIT(30) +#define FTGMAC100_TXDES1_TXIC BIT(31)
/* * Receive descriptor, aligned to 16 bytes @@ -211,20 +211,20 @@ struct ftgmac100_rxdes { } __attribute__ ((aligned(16)));
#define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) -#define FTGMAC100_RXDES0_EDORR (1 << 15) -#define FTGMAC100_RXDES0_MULTICAST (1 << 16) -#define FTGMAC100_RXDES0_BROADCAST (1 << 17) -#define FTGMAC100_RXDES0_RX_ERR (1 << 18) -#define FTGMAC100_RXDES0_CRC_ERR (1 << 19) -#define FTGMAC100_RXDES0_FTL (1 << 20) -#define FTGMAC100_RXDES0_RUNT (1 << 21) -#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22) -#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23) -#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24) -#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25) -#define FTGMAC100_RXDES0_LRS (1 << 28) -#define FTGMAC100_RXDES0_FRS (1 << 29) -#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31) +#define FTGMAC100_RXDES0_EDORR BIT(15) +#define FTGMAC100_RXDES0_MULTICAST BIT(16) +#define FTGMAC100_RXDES0_BROADCAST BIT(17) +#define FTGMAC100_RXDES0_RX_ERR BIT(18) +#define FTGMAC100_RXDES0_CRC_ERR BIT(19) +#define FTGMAC100_RXDES0_FTL BIT(20) +#define FTGMAC100_RXDES0_RUNT BIT(21) +#define FTGMAC100_RXDES0_RX_ODD_NB BIT(22) +#define FTGMAC100_RXDES0_FIFO_FULL BIT(23) +#define FTGMAC100_RXDES0_PAUSE_OPCODE BIT(24) +#define FTGMAC100_RXDES0_PAUSE_FRAME BIT(25) +#define FTGMAC100_RXDES0_LRS BIT(28) +#define FTGMAC100_RXDES0_FRS BIT(29) +#define FTGMAC100_RXDES0_RXPKT_RDY BIT(31)
#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20) @@ -232,11 +232,11 @@ struct ftgmac100_rxdes { #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20) #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20) #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20) -#define FTGMAC100_RXDES1_LLC (1 << 22) -#define FTGMAC100_RXDES1_DF (1 << 23) -#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24) -#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25) -#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26) -#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27) +#define FTGMAC100_RXDES1_LLC BIT(22) +#define FTGMAC100_RXDES1_DF BIT(23) +#define FTGMAC100_RXDES1_VLANTAG_AVAIL BIT(24) +#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR BIT(25) +#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26) +#define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27)
#endif /* __FTGMAC100_H */