-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 2019年5月16日 19:58 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: M.h. Lian minghuan.lian@nxp.com; Z.q. Hou zhiqiang.hou@nxp.com; Mingkai Hu mingkai.hu@nxp.com; Hongbo Wang hongbo.wang@nxp.com; York Sun york.sun@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com Subject: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode
Caution: EXT Email
Hi,
On Thu, May 16, 2019 at 7:02 PM Xiaowei Bao xiaowei.bao@nxp.com wrote:
From: Xiaowei Bao xiaowei.bao@nxp.com
Signed-off-by: hongbo.wang hongbo.wang@nxp.com Signed-off-by: Minghuan Lian Minghuan.Lian@nxp.com Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com
v2:
- Add the NXP copyright and make the function readability.
drivers/pci/pcie_layerscape.c | 117 +++++++++++++++++++++++++++-------------- drivers/pci/pcie_layerscape.h | 19 +++++-- 2 files changed, 91 insertions(+), 45 deletions(-)
Could you please support the PCIe EP mode using driver model? [Xiaowei Bao] do you mean that add a EP driver model to separate the RC and EP with their respective drivers? The purpose of adding EP support under u-boot is to configure the size of the BAR when the PCIE controller is used as an EP device, and to ensure that the configuration space of the EP can be accessed, so that when the RC scans the bus, the EP device can be scanned, and we also can do simple MEM read and write verification through the md command in u-boot shell. When entering the kernel, the kernel has its own PCIE EP framework, which will reinitialize the EP device, contain of the inbound and outbound window configure, MSI configuration and so no.
Regards, Bin