16 Dec
2014
16 Dec
'14
6:17 p.m.
On 12/02/2014 11:18 AM, York Sun wrote:
For DDR controller version 4.7 or newer, MRC_CYC (mode register set cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD is max(12nCK, 15ns) according to JEDEC spec.
DDR4 is not affected by this change.
Signed-off-by: York Sun yorksun@freescale.com
Change log v3: Add cast for using max() v2: Apply the change only to DDR controller newer than v4.7 Older DDRC needs to take into account of RDIMM for tMRD
Applied to u-boot-mpc85xx master, awaiting upstream.
York