Re: [U-Boot] [PATCH 4/7] riscv: delay initialization of caches and debug UART

On Tue, Feb 12, 2019 at 6:14 AM Lukas Auer lukas.auer@aisec.fraunhofer.de wrote:

Move the initialization of the caches and the debug UART until after board_init_f_init_reserve. This is in preparation for SMP support, where code prior to this point will be executed by all harts. This ensures that initialization will only be performed once for the main hart running U-Boot.

Signed-off-by: Lukas Auer lukas.auer@aisec.fraunhofer.de

arch/riscv/cpu/start.S | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)

Reviewed-by: Bin Meng bmeng.cn@gmail.com