Affects: DDR Description: Memory controller performance is not optimal with default internal target queue register values. Impact: Memory controller performance is not optimal. Workaround: Write a value of 63b2_0002h to address: 157_020Ch.
Signed-off-by: Yuan Yao yao.yuan@freescale.com --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- board/freescale/ls1021aqds/ls1021aqds.c | 10 ++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 10 ++++++++++ 3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index d34044a..21bd65b 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -221,7 +221,7 @@ struct ccsr_scfg { u32 scfgrevcr; u32 coresrencr; u32 pex2pmrdsr; - u32 ddrc1cr; + u32 eddrtqcfg; u32 ddrc2cr; u32 ddrc3cr; u32 ddrc4cr; diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index d6ef6ba..52bffc8 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -299,6 +299,16 @@ int board_early_init_f(void) out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
/* + * Memory controller require a register write before being enabled. + * Affects: DDR + * Register: EDDRTQCFG + * Description: Memory controller performance is not optimal with + * default internal target queue register values. + * Workaround: Write a value of 63b2_0002h to address: 157_020Ch. + */ + out_be32(&scfg->eddrtqcfg, 0x63b20002); + + /* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) */ diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index b7458a9..c565e91 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -501,6 +501,16 @@ int board_early_init_f(void) out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
/* + * Memory controller require a register write before being enabled. + * Affects: DDR + * Register: EDDRTQCFG + * Description: Memory controller performance is not optimal with + * default internal target queue register values. + * Workaround: Write a value of 63b2_0002h to address: 157_020Ch. + */ + out_be32(&scfg->eddrtqcfg, 0x63b20002); + + /* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) */