This patch adds support for ASTRO board(s) based on MCF5373L.
Signed-off-by: Wolfgang Wegner w.wegner@astro-kom.de --- There is another board (series) in the queue to be submitted, thus I added a subdirectory for all our boards.
Makefile | 12 + board/astro/mcf5373l/Makefile | 44 +++ board/astro/mcf5373l/astro.h | 39 +++ board/astro/mcf5373l/config.mk | 28 ++ board/astro/mcf5373l/fpga.c | 424 +++++++++++++++++++++++ board/astro/mcf5373l/mcf5373l.c | 204 +++++++++++ board/astro/mcf5373l/u-boot.lds | 142 ++++++++ board/astro/mcf5373l/update.c | 699 ++++++++++++++++++++++++++++++++++++++ include/configs/astro_mcf5373l.h | 516 ++++++++++++++++++++++++++++ 9 files changed, 2108 insertions(+), 0 deletions(-) create mode 100644 board/astro/mcf5373l/Makefile create mode 100644 board/astro/mcf5373l/astro.h create mode 100644 board/astro/mcf5373l/config.mk create mode 100644 board/astro/mcf5373l/fpga.c create mode 100644 board/astro/mcf5373l/mcf5373l.c create mode 100644 board/astro/mcf5373l/u-boot.lds create mode 100644 board/astro/mcf5373l/update.c create mode 100644 include/configs/astro_mcf5373l.h
diff --git a/Makefile b/Makefile index 75b2c1e..924e210 100644 --- a/Makefile +++ b/Makefile @@ -2263,6 +2263,18 @@ M5485HFE_config : unconfig TASREG_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 tasreg esd
+astro_mcf5373l_config \ +astro_mcf5373l_ram_config : unconfig + @if [ "$@" = "astro_mcf5373l_ram_config" ] ; then \ + echo "#define CONFIG_MONITOR_IS_IN_RAM" >> $(obj)include/config.h ; \ + echo "TEXT_BASE = 0x40020000" > $(obj)board/astro/mcf5373l/config.tmp ; \ + $(XECHO) "... for RAM boot ..." ; \ + else \ + echo "TEXT_BASE = 0x00000000" > $(obj)board/astro/mcf5373l/config.tmp ; \ + $(XECHO) "... for FLASH boot ..." ; \ + fi + @$(MKCONFIG) -a astro_mcf5373l m68k mcf532x mcf5373l astro + ######################################################################### ## MPC83xx Systems ######################################################################### diff --git a/board/astro/mcf5373l/Makefile b/board/astro/mcf5373l/Makefile new file mode 100644 index 0000000..e0b1bc6 --- /dev/null +++ b/board/astro/mcf5373l/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o fpga.o update.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/astro/mcf5373l/astro.h b/board/astro/mcf5373l/astro.h new file mode 100644 index 0000000..9478787 --- /dev/null +++ b/board/astro/mcf5373l/astro.h @@ -0,0 +1,39 @@ +#ifndef __ASTRO_H__ +#define __ASTRO_H__ + +int rs_serial_init(int port, int baud); +void astro_put_char(char ch); +int astro_is_char(void); +int astro_get_char(void); + +/* data structures used for communication (update.c) */ +typedef struct _s_karten_id { + char Kartentyp; + char Hardwareversion; + char Softwareversion; + char SoftwareSubversion; /* " ","a",.."z" */ + char FPGA_Version_Alt; + char FPGA_Version_Xil; +} s_karten_id; + +typedef struct { + unsigned char mode; + unsigned char deviation; + unsigned short freq; +} __attribute__ ((packed)) s_output_params; + +typedef struct { + unsigned short SatFreq; + unsigned char SatDatAllg; + unsigned short Symbolrate; + unsigned char Viterbirate; + unsigned char Symbolrate_L; + s_output_params output_params; + unsigned char Reserve; + unsigned char Kartenfehler; + unsigned short dummy_ts_id; + unsigned char dummy_pat_ver; + unsigned char dummy_sdt_ver; +} __attribute__ ((packed)) s_datensatz; + +#endif /* __ASTRO_H__ */ diff --git a/board/astro/mcf5373l/config.mk b/board/astro/mcf5373l/config.mk new file mode 100644 index 0000000..59752c1 --- /dev/null +++ b/board/astro/mcf5373l/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn bkuhn@metrowerks.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +echo "BOARD DIR = $(BOARDDIR)" +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c new file mode 100644 index 0000000..eb1bf49 --- /dev/null +++ b/board/astro/mcf5373l/fpga.c @@ -0,0 +1,424 @@ +/* + * (C) Copyright 2006 + * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH, + * w.wegner@astro-kom.de + * + * based on the files by + * Heiko Schocher, DENX Software Engineering, hs@denx.de + * and + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board + */ + +#include <common.h> +#include <watchdog.h> +#include <altera.h> +#include <ACEX1K.h> +#include <spartan3.h> +#include <command.h> +#include <asm/immap_5329.h> +#include "fpga.h" + +DECLARE_GLOBAL_DATA_PTR; + +int altera_pre_fn (int cookie) +{ + volatile gpio_t *gpiop = (volatile gpio_t *)MMAP_GPIO; + +/* first, set the required pins to GPIO function */ + /* PAR_T0IN -> GPIO */ + gpiop->par_timer &= 0xfc; + /* all QSPI pins -> GPIO */ + gpiop->par_qspi = 0x0000; + /* U0RTS, U0CTS -> GPIO */ + gpiop->par_uart &= 0xfff3; + /* all PWM pins -> GPIO */ + gpiop->par_pwm = 0x00; +/* next, set data direction registers */ + gpiop->pddr_timer = 0x01; + gpiop->pddr_qspi = 0x25; + gpiop->pddr_uart = 0x0c; + gpiop->pddr_pwm = 0x04; + +/* ensure other SPI peripherals are deselected */ + gpiop->ppd_uart = 0x08; + gpiop->ppd_qspi = 0x38; + +/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ + gpiop->pclrr_uart = 0xFB; +/* enable Altera configuration by clearing QSPI_CS2 and DT0IN */ + gpiop->pclrr_timer = 0xFE; + gpiop->pclrr_qspi = 0xDF; + return FPGA_SUCCESS; +} + +/* Set the state of CONFIG Pin */ +int altera_config_fn (int assert_config, int flush, int cookie) +{ + volatile gpio_t *gpiop = (volatile gpio_t *)MMAP_GPIO; + + if (assert_config) + gpiop->ppd_uart = 0x04; + else + gpiop->pclrr_uart = 0xFB; + return FPGA_SUCCESS; +} + +/* Returns the state of STATUS Pin */ +int altera_status_fn (int cookie) +{ + unsigned char reg; + volatile gpio_t *gpiop = (volatile gpio_t *)MMAP_GPIO; + + reg = (gpiop->ppd_pwm >> 3) & 0x01; + if (reg) { + return FPGA_FAIL; + } + return FPGA_SUCCESS; +} + +/* Returns the state of CONF_DONE Pin */ +int altera_done_fn (int cookie) +{ + unsigned char reg; + volatile gpio_t *gpiop = (volatile gpio_t *)MMAP_GPIO; + + reg = (gpiop->ppd_pwm >> 5) & 0x01; + if (reg) + return FPGA_FAIL; + return FPGA_SUCCESS; +} + +/* writes the complete buffer to the FPGA + writing the complete buffer in one function is much faster, + then calling it for every bit */ +int altera_write_fn (void *buf, size_t len, int flush, int cookie) +{ + size_t bytecount = 0; + volatile gpio_t *gpiop = (volatile gpio_t *)MMAP_GPIO; + unsigned char *data = (unsigned char *)buf; + unsigned char val = 0; + int i; + int len_40 = len / 40; + + while (bytecount < len) { + val = data[bytecount++]; + i = 8; + do { + gpiop->pclrr_qspi = 0xFB; + if (val & 0x01) + gpiop->ppd_qspi = 0x01; + else + gpiop->pclrr_qspi = 0xFE; + gpiop->ppd_qspi = 0x04; + val >>= 1; + i--; + } while (i > 0); + + if (bytecount % len_40 == 0) { +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + WATCHDOG_RESET (); +#endif +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + putc ('.'); /* let them know we are alive */ +#endif +#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC + if (ctrlc ()) + return FPGA_FAIL; +#endif + } + } + return FPGA_SUCCESS; +} + +/* called, when programming is aborted */ +int altera_abort_fn (int cookie) +{ + volatile gpio_t *gpiop = (volatile gpio_t *)MMAP_GPIO; + gpiop->ppd_qspi = 0x20; + gpiop->ppd_uart = 0x08; + return FPGA_SUCCESS; +} + +/* called, when programming was succesful */ +int altera_post_fn (int cookie) +{ + return altera_abort_fn (cookie); +} + +/* Note that these are pointers to code that is in Flash. They will be + * relocated at runtime. + * FIXME: relocation not yet working for coldfire, see below! + */ +Altera_CYC2_Passive_Serial_fns altera_fns = { + altera_pre_fn, + altera_config_fn, + altera_status_fn, + altera_done_fn, + altera_write_fn, + altera_abort_fn, + altera_post_fn +}; + +Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = { + {Altera_CYC2, + passive_serial, + 85903, + (void *)&altera_fns, + NULL, + 0} +}; + +/* + * Initialize the fpga. Return 1 on success, 0 on failure. + */ +int astro5373l_altera_load (void) +{ + int i; + + for (i = 0; i < CONFIG_FPGA_COUNT; i++) { +/* I did not yet manage to get relocation work properly, + * so set stuff here instead of static initialisation: */ + altera_fns.pre = altera_pre_fn; + altera_fns.config = altera_config_fn; + altera_fns.status = altera_status_fn; + altera_fns.done = altera_done_fn; + altera_fns.write = altera_write_fn; + altera_fns.abort = altera_abort_fn; + altera_fns.post = altera_post_fn; + altera_fpga[i].iface_fns = (void *)&altera_fns; + fpga_add (fpga_altera, &altera_fpga[i]); + } + return 1; +} + +/* + * Set the FPGA's PROG_B line to the specified level + */ +int xilinx_pgm_fn (int assert, int flush, int cookie) +{ + volatile gpio_t *gpiop = (volatile gpio_t *)MMAP_GPIO; + + if (assert) + gpiop->pclrr_uart = 0xFB; + else + gpiop->ppd_uart = 0x04; + return assert; +} + +/* + * Test the state of the active-low FPGA INIT line. Return 1 on INIT + * asserted (low). + */ +int xilinx_init_fn (int cookie) +{ + unsigned char state; + volatile gpio_t *gpiop = (volatile gpio_t *)MMAP_GPIO; + + state = (gpiop->ppd_pwm & 0x08) >> 3; + if (state) + return 0; + else + return 1; +} + +/* + * Test the state of the active-high FPGA DONE pin + */ +int xilinx_done_fn (int cookie) +{ + volatile gpio_t *gpiop = (volatile gpio_t *)MMAP_GPIO; + + return (gpiop->ppd_pwm & 0x20) >> 5; +} + +/* + * Abort an FPGA operation + */ +int xilinx_abort_fn (int cookie) +{ + volatile gpio_t *gpiop = (volatile gpio_t *)MMAP_GPIO; +/* ensure all SPI peripherals and FPGAs are deselected */ + gpiop->ppd_uart = 0x08; + gpiop->ppd_timer = 0x01; + gpiop->ppd_qspi = 0x38; + return FPGA_FAIL; +} + +/* + * FPGA pre-configuration function. Just make sure that + * FPGA reset is asserted to keep the FPGA from starting up after + * configuration. + */ +int xilinx_pre_config_fn (int cookie) +{ + volatile gpio_t *gpiop = (volatile gpio_t *)MMAP_GPIO; +/* first, set the required pins to GPIO function */ + /* PAR_T0IN -> GPIO */ + gpiop->par_timer &= 0xfc; + /* all QSPI pins -> GPIO */ + gpiop->par_qspi = 0x0000; + /* U0RTS, U0CTS -> GPIO */ + gpiop->par_uart &= 0xfff3; + /* all PWM pins -> GPIO */ + gpiop->par_pwm = 0x00; +/* next, set data direction registers */ + gpiop->pddr_timer = 0x01; + gpiop->pddr_qspi = 0x25; + gpiop->pddr_uart = 0x0c; + gpiop->pddr_pwm = 0x04; + +/* ensure other SPI peripherals are deselected */ + gpiop->ppd_uart = 0x08; + gpiop->ppd_qspi = 0x38; + gpiop->ppd_timer = 0x01; + +/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ + gpiop->pclrr_uart = 0xFB; +/* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */ + gpiop->pclrr_uart = 0xF7; + gpiop->pclrr_qspi = 0xDF; + return 0; +} + +/* + * FPGA post configuration function. Should perform a test if FPGA is running... + */ +int xilinx_post_config_fn (int cookie) +{ + int rc = 0; + + /* + * no test yet + */ + return rc; +} + +int xilinx_clk_fn (int assert_clk, int flush, int cookie) +{ + volatile gpio_t *gpiop = (volatile gpio_t *)MMAP_GPIO; + + if (assert_clk) + gpiop->ppd_qspi = 0x04; + else + gpiop->pclrr_qspi = 0xFB; + return assert_clk; +} + +int xilinx_wr_fn (int assert_write, int flush, int cookie) +{ + volatile gpio_t *gpiop = (volatile gpio_t *)MMAP_GPIO; + + if (assert_write) + gpiop->ppd_qspi = 0x01; + else + gpiop->pclrr_qspi = 0xFE; + return assert_write; +} + +int xilinx_fastwr_fn (void *buf, size_t len, int flush, int cookie) +{ + size_t bytecount = 0; + volatile gpio_t *gpiop = (volatile gpio_t *)MMAP_GPIO; + unsigned char *data = (unsigned char *)buf; + unsigned char val = 0; + int i; + int len_40 = len / 40; + + for (bytecount = 0; bytecount < len; bytecount++) { + val = *(data++); + for (i = 8; i > 0; i--) { + gpiop->pclrr_qspi = 0xFB; + if (val & 0x80) + gpiop->ppd_qspi = 0x01; + else + gpiop->pclrr_qspi = 0xFE; + gpiop->ppd_qspi = 0x04; + val <<= 1; + } + if (bytecount % len_40 == 0) { +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + WATCHDOG_RESET (); +#endif +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + putc ('.'); /* let them know we are alive */ +#endif +#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC + if (ctrlc ()) + return FPGA_FAIL; +#endif + } + } + return FPGA_SUCCESS; +} + +/* Note that these are pointers to code that is in Flash. They will be + * relocated at runtime. + * FIXME: relocation not yet working for coldfire, see below! + */ +Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = { + xilinx_pre_config_fn, + xilinx_pgm_fn, + xilinx_clk_fn, + xilinx_init_fn, + xilinx_done_fn, + xilinx_wr_fn, + 0, + xilinx_fastwr_fn +}; + +Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { + {Xilinx_Spartan3, + slave_serial, + XILINX_XC3S4000_SIZE, + (void *)&xilinx_fns, + 0} +}; + +/* + * Initialize the fpga. Return 1 on success, 0 on failure. + */ +int astro5373l_xilinx_load (void) +{ + int i; + + fpga_init (); + + for (i = 0; i < CONFIG_FPGA_COUNT; i++) { +/* I did not yet manage to get relocation work properly, + * so set stuff here instead of static initialisation: */ + xilinx_fns.pre = xilinx_pre_config_fn; + xilinx_fns.pgm = xilinx_pgm_fn; + xilinx_fns.clk = xilinx_clk_fn; + xilinx_fns.init = xilinx_init_fn; + xilinx_fns.done = xilinx_done_fn; + xilinx_fns.wr = xilinx_wr_fn; + xilinx_fns.bwr = xilinx_fastwr_fn; + xilinx_fpga[i].iface_fns = (void *)&xilinx_fns; + fpga_add (fpga_xilinx, &xilinx_fpga[i]); + } + return 1; +} diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c new file mode 100644 index 0000000..0c87128 --- /dev/null +++ b/board/astro/mcf5373l/mcf5373l.c @@ -0,0 +1,204 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * modified by Wolfgang Wegner w.wegner@astro-kom.de for ASTRO 5373l + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <command.h> +#include <asm/m5329.h> +#include <asm/immap_5329.h> + +/* needed for astro bus: */ +#include <asm/uart.h> +#include "astro.h" + +DECLARE_GLOBAL_DATA_PTR; +extern void uart_port_conf (void); + +extern int astro5373l_altera_load (void); +extern int astro5373l_xilinx_load (void); + +int checkboard (void) +{ + puts ("Board: "); + puts ("ASTRO MCF5373L (Urmel) Board\n"); + return 0; +} + +phys_size_t initdram (int board_type) +{ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + volatile sdram_t *sdp = (volatile sdram_t *)(MMAP_SDRAM); + +/* GPIO configuration for bus should be set correctly from reset, so we do not care! + * First, set up address space: at this point, we should be running from internal SRAM; + * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM, and do not care where it is + */ + sdp->cs0 = (CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018; +/* I am not sure from the data sheet, but it seems burst length has to be 8 + * for the 16 bit data bus we use; so these values are for BL = 8 + */ + sdp->cfg1 = 0x33211530; + sdp->cfg2 = 0x56570000; /* for BL = 4: 0x34330000 */ +/* send PrechargeALL, REF and IREF remain cleared! */ + sdp->ctrl = 0xE1462C02; + udelay (1); +/* refresh SDRAM twice */ + sdp->ctrl = 0xE1462C04; + udelay (1); + sdp->ctrl = 0xE1462C04; +/* init MR */ + sdp->mode = 0x008D0000; +/* initialize EMR */ + sdp->mode = 0x80010000; +/* wait until DLL is locked */ + udelay (1); +/* enable automatic refresh, lock mode register, clear iref and ipall */ + sdp->ctrl = 0x71462C00; +/* Dummy write to start SDRAM */ + *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0; +#endif + + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +} + +int testdram (void) +{ + printf ("DRAM test not implemented!\n"); + + return (0); +} + +#define UART_BASE MMAP_UART0 +int rs_serial_init (int port, int baud) +{ + volatile uart_t *uart; + u32 counter; + + switch (port) { + case 0: + uart = (volatile uart_t *)(MMAP_UART0); + break; + case 1: + uart = (volatile uart_t *)(MMAP_UART1); + break; + case 2: + uart = (volatile uart_t *)(MMAP_UART2); + break; + default: + uart = (volatile uart_t *)(MMAP_UART0); + } + + uart_port_conf (); + + /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ + uart->ucr = UART_UCR_RESET_RX; + uart->ucr = UART_UCR_RESET_TX; + uart->ucr = UART_UCR_RESET_ERROR; + uart->ucr = UART_UCR_RESET_MR; + __asm__ ("nop"); + + uart->uimr = 0; + + /* write to CSR: RX/TX baud rate from timers */ + uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK); + + uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE); + uart->umr = UART_UMR_SB_STOP_BITS_1; + + /* Setting up BaudRate */ + counter = (u32) (gd->bus_clk / (baud)); + counter >>= 5; + + /* write to CTUR: divide counter upper byte */ + uart->ubg1 = (u8) ((counter & 0xff00) >> 8); + /* write to CTLR: divide counter lower byte */ + uart->ubg2 = (u8) (counter & 0x00ff); + + uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED); + + return (0); +} + +void astro_put_char (char ch) +{ + volatile uart_t *uart; + int i; + + uart = (volatile uart_t *)(MMAP_UART0); + /* Wait for last character to go. */ + for (i = 0; (i < 0x10000); i++) + if (uart->usr & UART_USR_TXRDY) + break; + uart->utb = ch; + + return; +} + +int astro_is_char (void) +{ + volatile uart_t *uart; + + uart = (volatile uart_t *)(MMAP_UART0); + return (uart->usr & UART_USR_RXRDY); +} + +int astro_get_char (void) +{ + volatile uart_t *uart; + + uart = (volatile uart_t *)(MMAP_UART0); + while (!(uart->usr & UART_USR_RXRDY)) ; + return uart->urb; +} + +int misc_init_r (void) +{ + int retval = 0; + + puts ("Configure Xilinx FPGA..."); + retval = astro5373l_xilinx_load (); + if (!retval) { + puts ("failed!\n"); + return retval; + } + puts ("done\n"); + + puts ("Configure Altera FPGA..."); + retval = astro5373l_altera_load (); + if (!retval) { + puts ("failed!\n"); + return retval; + } + puts ("done\n"); + + return retval; +} + +#ifdef CONFIG_SYS_FLASH_CFI +void sync (void) +{ + /* This sync function is PowerPC instruction, + coldfire does not have this instruction. Dummy function */ +} +#endif diff --git a/board/astro/mcf5373l/u-boot.lds b/board/astro/mcf5373l/u-boot.lds new file mode 100644 index 0000000..a9a4e0a --- /dev/null +++ b/board/astro/mcf5373l/u-boot.lds @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf532x/start.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o (.text) + + *(.text) +/* *(.fixup)*/ + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/astro/mcf5373l/update.c b/board/astro/mcf5373l/update.c new file mode 100644 index 0000000..ac57816 --- /dev/null +++ b/board/astro/mcf5373l/update.c @@ -0,0 +1,699 @@ +/* + * (C) Copyright 2006-2009 + * Adnan El-Bardawil a.el-bardawil@astro-kom.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define DEBUG_INFO 1 +#define DEBUG_ERROR 1 + +/* dummy software version to signal card is in boot loader */ +#define SOFTWARE_VERSION 0x00 +#define SOFTWARE_SUBVERSION ' ' + +#define CMD_INIT 0 +#define CMD_NEW 1 +#define CMD_TX 2 +#define CMD_RX 3 +#define CMD_OK 4 +#define CMD_FAIL 5 +#define CMD_CH_RX 6 +#define CMD_TX_END 7 +#define CMD_RX_END 8 +#define CMD_TX_RDY 9 +#define CMD_RX_RDY 10 +#define CMD_RX_ERROR 11 + +#define INT_CMD_IDLE 0 +#define INT_CMD_WR_CONF 1 +#define INT_CMD_INIT_LVL 2 +#define INT_CMD_INIT_PID 4 +#define INT_CMD_INIT_UKW 8 +#define INT_CMD_SEL_SERV 16 +#define INT_CMD_FLASH_MODE 32 +#define INT_CMD_WRITE_FLASH 64 +#define INT_CMD_RESTART 128 +#define INT_CMD_PROG_START 256 +#define INT_CMD_PROG_READY 512 +#define INT_CMD_INIT_TIME 1024 + +#define FL_STAT_IDLE 0 +#define FL_STAT_ERASE 1 +#define FL_STAT_PROG 2 +#define FL_STAT_ERROR 4 + +#include <common.h> +#include <watchdog.h> +#include <command.h> +#include <asm/m5329.h> +#include <asm/immap_5329.h> +#include <flash.h> +#include "astro.h" + +#include <asm/uart.h> + +DECLARE_GLOBAL_DATA_PTR; + +/*----------------------------------------------------------------------- + * UART update subcommand codes + */ + +#define F_Daten_Speichern 0x00 /* save parameters on card */ +#define F_Daten_Lesen 0x01 /* read parameters */ +#define F_Karteninfo_Lesen 0x10 /* read 5 Byte card information */ +#define F_Kartenfehler_Lesen 0x11 /* read 4 Byte card error */ +#define F_Transparente_Daten 0x20 /* length byte + data */ + +#define SC_Prepare_for_Flash_Data 0xc0 +#define SC_Flash_Data 0xc1 +#define SC_Clear_CRC 0xc2 +#define SC_Check_CRC 0xc3 +#define SC_Restart 0xc4 + +typedef struct { + unsigned char command; + unsigned char length; + unsigned char subcommand; + unsigned char channel; +} rcv_cmd_s; + +s_karten_id Karteninformation; + +s_output_params output_params[2]; + +struct { + s_datensatz A; + s_datensatz B; +} Datensatz; + +typedef struct { + int cnt; + int stat; +} command_s; + +typedef struct { + int cnt; + int length; + unsigned char *buffer; +} comm_status; + +const ulong fl_base[3] = { 0x80000, 0x540000, 0x6c0000 }; +const char fl_type_str[3][6] = { "Kernel", "Xilinx", "Altera" }; + +/* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + +unsigned long crc, crc_count; + +/* CRC divisor value */ +#define CRC_POLYNOM 0x800500 + +void do_crc (unsigned char data) +{ + unsigned char count; + + crc |= data; + for (count = 0; count < 8; count++) { + crc <<= 1; + if (crc & 0x1000000) + crc ^= CRC_POLYNOM; + } + crc_count++; +} + +int dez2hex (int in) +{ + int out; + + out = 16 * (in / 10); + out += (in % 10); + return out; +} + +/* somehow inlining the function failed, so we use a define instead */ +#define astro_read_select(dummy) \ + (((((volatile eport_t *)MMAP_EPORT)->pdr >> 6) & 0x01) == 0x0) + +static unsigned char flash_buffer[0x10000]; +static unsigned long flash_data_length, flash_data_count; +static unsigned long flash_prog_count, flash_sect_count; +static unsigned char flash_data_type, crc_en, crc_status; +static int flash_prog_stat; +static ulong fl_adr, fl_sector; +static unsigned char uart_buffer[64]; + +void fl_prog (ushort int_command) +{ + int s, i; + + /* nothing to do if we are not in flash mode */ + if ((int_command & INT_CMD_FLASH_MODE) == 0x0) + return; + + fl_adr = fl_base[flash_data_type] + flash_prog_count; + fl_sector = fl_adr >> 17; + + if (flash_prog_stat == FL_STAT_IDLE) { + if (((flash_prog_count & 0x1ffff) == 0) && + ((flash_prog_count >> 17) == flash_sect_count)) { + flash_protect (FLAG_PROTECT_CLEAR, fl_adr, + fl_adr + 0x1ffff, flash_info); + s = flash_erase_nb (flash_info, fl_sector); + flash_prog_stat = FL_STAT_ERASE; + } + else if ((flash_data_count >= (flash_prog_count + 64)) + || ((int_command & INT_CMD_WRITE_FLASH) + && (flash_data_count > flash_prog_count))) { + s = write_buff_nb (flash_info, + flash_buffer + + (flash_prog_count & 0xffff), + fl_adr, 64); + flash_prog_stat = FL_STAT_PROG; + } + } + else if (flash_prog_stat == FL_STAT_ERASE) { + s = flash_full_status_check_nb (flash_info, fl_sector, + 0, "erase"); + if (s != ERR_BUSY) { + if (s == ERR_OK) { + flash_sect_count++; + flash_prog_stat = FL_STAT_IDLE; + } + else + flash_prog_stat = FL_STAT_ERROR; + } + } + else if (flash_prog_stat == FL_STAT_PROG) { + s = flash_full_status_check_nb (flash_info, fl_sector, + 0, "write"); + if (s != ERR_BUSY) { + if (s == ERR_OK) { + flash_prog_stat = FL_STAT_IDLE; + for (i = 0; i < 64; i++) + if (flash_buffer + [(flash_prog_count + i) + & 0xffff] != + *((unsigned char *)fl_adr + + i)) + flash_prog_stat = + FL_STAT_ERROR; + if ((flash_prog_count & 0xfff) == 0) + printf ("."); + flash_prog_count += 64; + if (((flash_prog_count & 0x1ffff) == 0) + || + ((int_command & INT_CMD_WRITE_FLASH) + && (flash_data_count <= + flash_prog_count))) { + flash_protect (FLAG_PROTECT_SET, + fl_adr & 0xfffe0000, + fl_adr | 0x1ffff, + flash_info); + } + } + else + flash_prog_stat = FL_STAT_ERROR; + } + } +} + +void handle_rx_char (unsigned char rx_data, command_s *cmd, + int *rcv_cnt, rcv_cmd_s *rcv_cmd, + comm_status *rx_stat) +{ + volatile uart_t *uart; + + uart = (volatile uart_t *)(MMAP_UART0); + if (uart->usr & UART_USR_OE) { + if (DEBUG_ERROR) + printf ("UART FIFO Overrun Error!"); + uart->usr = UART_UCR_RESET_ERROR | UART_UCR_RESET_RX; + cmd->stat = CMD_RX_ERROR; + } + if (cmd->stat == CMD_INIT) { + if (*rcv_cnt == 0) { + /* First received Byte is the Command */ + rcv_cmd->command = rx_data; + /* non-Transparent Data: start Command Processing */ + if (rcv_cmd->command != F_Transparente_Daten) { + cmd->stat = CMD_NEW; + cmd->cnt++; + } + else + (*rcv_cnt)++; + } + else { + /* Length and Subcommand for Transparent Data */ + if (*rcv_cnt == 1) { + rcv_cmd->length = rx_data; + (*rcv_cnt)++; + } + else { + rcv_cmd->subcommand = rx_data; + cmd->stat = CMD_NEW; + cmd->cnt++; + } + } + } + else if ((cmd->stat == CMD_RX) || (cmd->stat == CMD_RX_END)) { + /* Store received Data to Rx Buffer */ + *(rx_stat->buffer + (rx_stat->cnt)) = rx_data; + if (crc_en) + do_crc (rx_data); + (rx_stat->cnt)++; + if (rx_stat->cnt == rx_stat->length) { + cmd->stat = (cmd->stat == CMD_RX_END) ? + CMD_INIT : CMD_RX_RDY; + } + } + else if (cmd->stat == CMD_CH_RX) + rcv_cmd->channel = rx_data; +} + +/* handle a transparent data command; these are used for software update + * return value is 1 if cmd_stat is set to CMD_INIT to let caller decide + * to reset the receive count, else 0. + */ +int handle_transparent_command (command_s *cmd, rcv_cmd_s *rcv_cmd, + comm_status *rx_stat, comm_status *tx_stat, + unsigned short *int_command) +{ + int i; + ulong ext_crc; + + switch (rcv_cmd->subcommand) { +/***************************************************************************/ +/** Prepare for Flash Data **/ +/***************************************************************************/ + case SC_Prepare_for_Flash_Data: + + if (cmd->stat == CMD_NEW) { + rx_stat->buffer = uart_buffer; + rx_stat->length = 5; + rx_stat->cnt = 0; + cmd->stat = CMD_RX; + } + else if (cmd->stat == CMD_RX_RDY) { + for (i = 0; i < 4; i++) + flash_data_length = (flash_data_length << 8) + + uart_buffer[i + 1]; + flash_data_type = uart_buffer[0]; +#if DEBUG_INFO + printf (" -- Flash Programming Initialized -- \n"); + printf (" -- Receiving %lu Bytes of type ", + flash_data_length); + for (i = 0; i < 6; i++) + printf ("%c", fl_type_str[flash_data_type][i]); + printf (" [0x%lx]\n", fl_base[flash_data_type]); +#endif + uart_buffer[0] = rcv_cmd->command; + uart_buffer[1] = 1; + uart_buffer[2] = rcv_cmd->subcommand; + tx_stat->buffer = uart_buffer; + tx_stat->length = 3; + tx_stat->cnt = 0; + cmd->stat = CMD_TX; + } + else if (cmd->stat == CMD_TX_RDY) { + crc_count = 0; + crc = 0; + flash_data_count = 0; + flash_prog_count = 0; + flash_sect_count = 0; + flash_prog_stat = FL_STAT_IDLE; + crc_en = 0; + *int_command = INT_CMD_FLASH_MODE; + cmd->stat = CMD_INIT; + return 1; + } + break; +/***************************************************************************/ +/** Receive Flash Data **/ +/***************************************************************************/ + case SC_Flash_Data: + if (cmd->stat == CMD_NEW) { + rx_stat->buffer = flash_buffer + + (flash_data_count & 0xffff); + rx_stat->length = rcv_cmd->length - 1; + rx_stat->cnt = 0; + cmd->stat = CMD_RX; + crc_en = 1; + } + else if (cmd->stat == CMD_RX_RDY) { + crc_en = 0; + flash_data_count += rcv_cmd->length - 1; + cmd->stat = CMD_INIT; + return 1; + } + break; +/***************************************************************************/ +/** Clear CRC **/ +/***************************************************************************/ + case SC_Clear_CRC: + if (cmd->stat == CMD_NEW) { + uart_buffer[0] = rcv_cmd->command; + uart_buffer[1] = 1; + uart_buffer[2] = rcv_cmd->subcommand; + tx_stat->buffer = uart_buffer; + tx_stat->length = 3; + tx_stat->cnt = 0; + cmd->stat = CMD_TX_END; + crc_count = 0; + crc = 0; + } + break; +/***************************************************************************/ +/** Check_CRC -> Write to Flash **/ +/***************************************************************************/ + case SC_Check_CRC: + if (cmd->stat == CMD_NEW) { + rx_stat->buffer = uart_buffer; + rx_stat->length = 2; + rx_stat->cnt = 0; + cmd->stat = CMD_RX; + } + else if (cmd->stat == CMD_RX_RDY) { + if ((flash_data_count <= flash_prog_count) + || (flash_prog_stat == FL_STAT_ERROR)) { + crc_status = 0; + ext_crc = (uart_buffer[0] << 8) | + uart_buffer[1]; + if (uart_buffer[0] != ((crc >> 16) & 0xff)) + crc_status = 1; + if (uart_buffer[1] != ((crc >> 8) & 0xff)) + crc_status = 1; + if (flash_prog_stat == FL_STAT_ERROR) + crc_status |= 2; + uart_buffer[0] = rcv_cmd->command; + uart_buffer[1] = 4; + uart_buffer[2] = rcv_cmd->subcommand; + uart_buffer[3] = (crc >> 16); + uart_buffer[4] = (crc >> 8); + uart_buffer[5] = crc_status; +#if DEBUG_INFO + printf (" CRC %u / %lu of %lu kB \n", + crc_status, + (flash_data_count >> 10), + (flash_data_length >> 10)); +#endif + tx_stat->buffer = uart_buffer; + tx_stat->length = 6; + tx_stat->cnt = 0; + cmd->stat = CMD_TX_END; + if (crc_status) { + flash_prog_count = + flash_data_count = + (flash_data_count & 0xffff0000) + - 0x10000; + flash_prog_stat = FL_STAT_IDLE; + *int_command = INT_CMD_FLASH_MODE; + } + } + if (flash_data_count & 0xffff) + *int_command |= INT_CMD_WRITE_FLASH; + } + break; +/***************************************************************************/ +/** Restart **/ +/***************************************************************************/ + case SC_Restart: + if (cmd->stat == CMD_NEW) { + uart_buffer[0] = rcv_cmd->command; + uart_buffer[1] = 1; + uart_buffer[2] = rcv_cmd->subcommand; + tx_stat->buffer = uart_buffer; + tx_stat->length = 3; + tx_stat->cnt = 0; + cmd->stat = CMD_TX; + crc_count = 0; + crc = 0; + } + else if (cmd->stat == CMD_TX_RDY) { + *int_command = INT_CMD_RESTART; + cmd->stat = CMD_INIT; + return 1; + } + break; + } + return 0; +} + +/* handle a general command (i.e. status and version information query) + * return value is always 0 except for transparent data where the + * return code is passed through to allow caller reset receive count. + */ +int handle_command (command_s *cmd, rcv_cmd_s *rcv_cmd, comm_status *rx_stat, + comm_status *tx_stat, unsigned short *int_command) +{ + int rv = 0; + + switch (rcv_cmd->command) { + +/***************************************************************************/ +/** Kartenfehler lesen **/ +/***************************************************************************/ + case F_Kartenfehler_Lesen: +#if DEBUG_INFO + printf ("Kartenfehler lesen\n"); +#endif + uart_buffer[0] = 0; + uart_buffer[1] = 0; + uart_buffer[2] = 0; + uart_buffer[3] = 0; + tx_stat->buffer = uart_buffer; + tx_stat->length = 4; + tx_stat->cnt = 0; + + cmd->stat = CMD_TX_END; + break; + +/***************************************************************************/ +/** Betriebsdaten lesen **/ +/***************************************************************************/ + case F_Daten_Lesen: + if (cmd->stat == CMD_NEW) { +#if DEBUG_INFO + printf ("Datensatz lesen\n"); +#endif + tx_stat->buffer = (unsigned char *) &Datensatz.A; + Datensatz.A.output_params = output_params[0]; + cmd->stat = CMD_TX; + } + else if (cmd->stat == CMD_TX_RDY) { + tx_stat->buffer = (unsigned char *) &Datensatz.B; + Datensatz.B.output_params = output_params[1]; + cmd->stat = CMD_TX_END; + } + tx_stat->length = 13; + tx_stat->cnt = 0; + break; + +/***************************************************************************/ +/** Karteninfo lesen **/ +/***************************************************************************/ + case F_Karteninfo_Lesen: +#if DEBUG_INFO + printf ("Karteninfo lesen\n"); +#endif + Karteninformation.Softwareversion = + ((*int_command) & INT_CMD_FLASH_MODE) ? + 0xEE : SOFTWARE_VERSION; + + tx_stat->buffer = (unsigned char *)&Karteninformation; + tx_stat->length = 5; + tx_stat->cnt = 0; + cmd->stat = CMD_TX_END; + break; + + case F_Transparente_Daten: + rv = handle_transparent_command (cmd, rcv_cmd, rx_stat, + tx_stat, int_command); + break; + } + return rv; +} + +/* transmit data prepared in comm_status structure */ +void transmit_buffer(comm_status *tx_stat) +{ + while (tx_stat->cnt < tx_stat->length) { + astro_put_char (tx_stat->buffer[tx_stat->cnt]); + tx_stat->cnt++; + } +} + +int do_update (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + unsigned char rx_data; + + comm_status rx_stat, tx_stat; + command_s cmd; + int rcv_cnt, i; + rcv_cmd_s rcv_cmd; + unsigned short int_command; + + int select, old_select, got_char; + volatile eport_t *eport = (volatile eport_t *)MMAP_EPORT; + volatile gpio_t *gpio = (volatile gpio_t *)MMAP_GPIO; + + volatile uart_t *uart; + char *env_string; + + uart = (volatile uart_t *)(MMAP_UART0); + + cmd.cnt = 0; + + /* we set some dummy parameters to make the protocol work */ + Karteninformation.Kartentyp = ASTRO_ID; + env_string = getenv ("loaderversion"); + if (env_string != NULL) { + i = (int)simple_strtol (env_string, NULL, 10); + Karteninformation.Hardwareversion = dez2hex (i); + } + else + Karteninformation.Hardwareversion = 0x10; + Karteninformation.Softwareversion = SOFTWARE_VERSION; + Karteninformation.SoftwareSubversion = SOFTWARE_SUBVERSION; + Karteninformation.FPGA_Version_Alt = 0x12; + Karteninformation.FPGA_Version_Xil = 0x13; + + Datensatz.A.Symbolrate = 0x5027; + Datensatz.A.Viterbirate = 0x34; + Datensatz.A.SatFreq = 0x6616; + Datensatz.A.Kartenfehler = 0; + + Datensatz.B.Symbolrate = 0x5027; + Datensatz.B.Viterbirate = 0x34; + Datensatz.B.SatFreq = 0x6616; + Datensatz.B.Kartenfehler = 0; + + puts ("Initializing serial port to ASTRO-Bus...\n"); + /* init serial port */ + rs_serial_init (0, 2400); + /* set UART pin for UART */ + gpio->par_uart |= 0x0003; + /* set select pin as GPIO */ + gpio->par_irq &= 0x0FF0; + /* set select pin as input */ + eport->pdr &= 0xBF; + /* set interrupt to both falling and rising edge + * (no IRQ used, though) + */ + eport->par |= 0x3000; + + int_command = 0; + + rcv_cnt = 0; + cmd.stat = CMD_INIT; + old_select = astro_read_select (); + + while (int_command != INT_CMD_RESTART) { + +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + WATCHDOG_RESET (); +#endif + +/***************************************************************************/ +/** Flash program routine **/ +/***************************************************************************/ + + fl_prog (int_command); + +/***************************************************************************/ +/** UART Card Select Routine **/ +/***************************************************************************/ + + /* Write ID on Card Select */ + + select = astro_read_select (); + if ((select) && (!old_select)) { + /* set low baud rate for ID only */ + rs_serial_init (0, 2400); + astro_put_char (ASTRO_ID); + + /* Wait for TX finished before switching baudrate */ + while ((uart->usr & UART_USR_TXEMP) == 0) { + } + + /* set high baud rate */ + rs_serial_init (0, 115200); + // Reset the Receive Byte Counter + rcv_cnt = 0; + cmd.stat = CMD_INIT; + } + else if ((!select) && old_select) { + if (cmd.stat != CMD_INIT) { + cmd.stat = CMD_FAIL; + if (DEBUG_ERROR) + printf ("Command %u: 0x%02x failed\n", + cmd.cnt, rcv_cmd.command); + } + } + + old_select = select; + + got_char = astro_is_char (); + if (got_char) + rx_data = astro_get_char (); + + if (select) { +/***************************************************************************/ +/** UART RX Routine **/ +/***************************************************************************/ + if (got_char) + handle_rx_char (rx_data, &cmd, &rcv_cnt, + &rcv_cmd, &rx_stat); + +/***************************************************************************/ +/** Command Control Routine **/ +/***************************************************************************/ + if ((cmd.stat == CMD_NEW) + || (cmd.stat == CMD_CH_RX) + || (cmd.stat == CMD_RX_RDY) + || (cmd.stat == CMD_TX_RDY)) { + i = handle_command (&cmd, &rcv_cmd, + &rx_stat, &tx_stat, + &int_command); + if(i) + rcv_cnt = 0; + } + +/***************************************************************************/ +/** UART TX Routine **/ +/***************************************************************************/ + if ((cmd.stat == CMD_TX) || (cmd.stat == CMD_TX_END)) { + transmit_buffer(&tx_stat); + if (cmd.stat == CMD_TX_END) { + /* Reset the Receive Byte Counter */ + rcv_cnt = 0; + cmd.stat = CMD_INIT; + } + else + cmd.stat = CMD_TX_RDY; + } + } + } + return 0; +} + +U_BOOT_CMD (update, 2, 1, do_update, + "update - update function information\n", + "\n - print information for update\n" + "update N\n - print information for update # N\n"); diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h new file mode 100644 index 0000000..2ce80f8 --- /dev/null +++ b/include/configs/astro_mcf5373l.h @@ -0,0 +1,516 @@ +/* + * Configuation settings for the Sentec Cobra Board. + * + * (C) Copyright 2003 Josef Baumgartner josef.baumgartner@telex.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* configuration for ASTRO "Urmel" board. + * Originating from Cobra5272 configuration, messed up by + * Wolfgang Wegner w.wegner@astro-kom.de + * Please do not bother the original author with bug reports + * concerning this file. + */ + +/* --- + * board/config.h - configuration options, board specific + * --- + */ + +#ifndef _CONFIG_ASTRO_MCF5373L_H +#define _CONFIG_ASTRO_MCF5373L_H + +/* either of CONFIG_ASTRO_V532, CONFIG_ASTRO_V512 or + * CONFIG_ASTRO_TWIN7S2 has to be defined! + */ +#define CONFIG_ASTRO_V532 1 + +#if CONFIG_ASTRO_V532 +#define ASTRO_ID 0xF8 +#elif CONFIG_ASTRO_V512 +#define ASTRO_ID 0xFA +#elif CONFIG_ASTRO_TWIN7S2 +#define ASTRO_ID 0xF9 +#elif CONFIG_ASTRO_V912 +#define ASTRO_ID 0xFC +#elif CONFIG_ASTRO_COFDMDUOS2 +#define ASTRO_ID 0xFB +#else +#error No card type defined! +#endif + +/* --- + * Define processor + * possible values for Urmel board: only Coldfire M5373 processor supported + * (please do not change) + * --- + */ + +/* it seems not clear yet which processor defines we should use */ +#define CONFIG_MCF537x /* define processor family */ +#define CONFIG_MCF532x /* define processor family */ +#define CONFIG_M5373 /* define processor type */ +#define CONFIG_ASTRO5373L /* define board type */ + +/* Command line configuration */ +#include <config_cmd_default.h> + +/* --- + * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different + * bootloader residing in flash or loaded via BDM + * --- + */ + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define ENABLE_NETWORK 0 +#define ENABLE_JFFS 0 +#else +#define ENABLE_NETWORK 1 +#define ENABLE_JFFS 1 +#endif + +/* --- + * Define which commmands should be available at u-boot command prompt + * --- + */ + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_XIMG +#if ENABLE_NETWORK +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#else +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#endif +#if ENABLE_JFFS +#define CONFIG_CMD_JFFS2 +#endif +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_FPGA +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#if ENABLE_NETWORK +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN + +# define CONFIG_SYS_FEC0_PINMUX 0 +# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif +#endif + +#define CONFIG_MCFRTC +#undef RTC_DEBUG + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SPEED 80000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +/* --- + * Defines processor clock - important for correct timings concerning serial + * interface etc. + * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms + * --- + */ + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CLK 80000000 +#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 +#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ + +#define CONFIG_SYS_CORE_SRAM_SIZE 0x8000 +#define CONFIG_SYS_CORE_SRAM 0x80000000 + +#define CONFIG_SYS_UNIFY_CACHE + +/* --- + * Enable use of Ethernet + * --- + */ + +/* ethernet could be useful for debugging */ +/* #define FEC_ENET */ + +/* --- + * Define baudrate for UART1 (console output, tftp, ...) + * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud + * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command + * interface + * --- + */ + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (2) +#define CONFIG_SYS_UART2_ALT3_GPIO + +/* --- + * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change + * timeout acc. to your needs + * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000 + * for 10 sec + * --- + */ + +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */ +#endif + +/* --- + * Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + * --- + */ + +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_ENV_OFFSET 0x1FF8000 +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_IN_FLASH 1 +#else +/* environment in RAM - I hope we can thus use a single PC-based application + to load an image, load U-Boot, load an environment and then start U-Boot + to execute the commands from the environment. Just the feedback is still + missing then... */ +#define CONFIG_ENV_ADDR 0x40060000 +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_IN_FLASH 1 +#endif + +// here we put our FPGA configuration... +#define CONFIG_MISC_INIT_R 1 + +/* + *----------------------------------------------------------------------------- + * Define user parameters that have to be customized most likely + *----------------------------------------------------------------------------- + */ + +/* AUTOBOOT settings - booting images automatically by u-boot after power on */ + +/* beware - watchdog is not service during autoboot delay time! */ +/* used for autoboot, delay in seconds u-boot will wait before starting + defined (auto-)boot command, setting to -1 disables delay, setting to + 0 will too prevent access to u-boot command interface: u-boot then has + to be reflashed */ +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_BOOTDELAY 1 +#else +#define CONFIG_BOOTDELAY 1 +#endif + +/* The following settings will be contained in the environment block ; if you +want to use a neutral environment all those settings can be manually set in +u-boot: 'set' command */ + +#define _QUOTEME(x) #x +#define QUOTEME(x) _QUOTEME(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loaderversion=11\0" \ + "card_id="QUOTEME(ASTRO_ID)"\0" \ + "alterafile=0\0" \ + "xilinxfile=0\0" \ + "xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&fpga load 0 0x41000000 $filesize\0" \ + "alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&fpga load 1 0x41000000 $filesize\0" \ + "env_default=1\0" \ + "env_check=if test $env_default -eq 1; then setenv env_default 0;saveenv;fi\0" + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_BOOTCOMMAND "" /* Autoboot command, please enter a valid image address in flash */ +#else +#if CONFIG_ASTRO_V532 +#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;run xilinxload&&run alteraload&&bootm 0x80000;update;reset" +#else +#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;run xilinxload&&bootm 0x80000;update;reset" +#endif +#endif + +/* default bootargs that are considered during boot */ +#define CONFIG_BOOTARGS " console=ttyS2,115200 rootfstype=romfs loaderversion=$loaderversion" + +/* User network settings */ + +#define CONFIG_ETHADDR 00:00:00:00:00:09 /* default ethernet MAC addr. */ +#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */ +#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */ + +#define CONFIG_SYS_PROMPT "URMEL > " /* Layout of u-boot prompt*/ + +#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address +from which user programs will be started */ + +/*---*/ + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ + +#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_FPGA_COUNT 1 +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN3 +#define CONFIG_FPGA_ALTERA +#define CONFIG_FPGA_CYCLON2 +#define CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_SYS_FPGA_WAIT 1000 + +/* + *----------------------------------------------------------------------------- + * End of user parameters to be customized + *----------------------------------------------------------------------------- + */ + +/* --- + * Defines memory range for test + * --- + */ + +#define CONFIG_SYS_MEMTEST_START 0x400 +#define CONFIG_SYS_MEMTEST_END 0x380000 + +/* --- + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * --- + */ + +/* --- + * Base register address + * --- + */ + +#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ + +/* --- + * System Conf. Reg. & System Protection Reg. + * --- + */ + +#define CONFIG_SYS_SCR 0x0003; +#define CONFIG_SYS_SPR 0xffff; + +/* --- + * Ethernet settings + * --- + */ + +#if ENABLE_NETWORK +#define CONFIG_SYS_DISCOVER_PHY +#define CONFIG_SYS_ENET_BD_BASE 0x780000 +#endif + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in internal SRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * + * WW: please note that this can not be 0 for some processors... + * the MCF5373 can only start at 0x40000000 to 0x7FF00000 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - Flash 32MB (first 16MB) + * CS1 - Flash 32MB (second half) + * CS2 - FPGA + * CS3 - FPGA + * CS4 - Available + * CS5 - Available + */ +#define CONFIG_SYS_CS0_BASE 0 +#define CONFIG_SYS_CS0_MASK 0x00ff0001 +#define CONFIG_SYS_CS0_CTRL 0x00001fc0 + +#define CONFIG_SYS_CS1_BASE 0x01000000 +#define CONFIG_SYS_CS1_MASK 0x00ff0001 +#define CONFIG_SYS_CS1_CTRL 0x00001fc0 + +#define CONFIG_SYS_CS2_BASE 0x20000000 +#define CONFIG_SYS_CS2_MASK 0x00ff0001 +#define CONFIG_SYS_CS2_CTRL 0x0000fec0 + +#define CONFIG_SYS_CS3_BASE 0x21000000 +#define CONFIG_SYS_CS3_MASK 0x00ff0001 +#define CONFIG_SYS_CS3_CTRL 0x0000fec0 + +/* + *------------------------------------------------------------------------- + * RAM SIZE (is defined above) + *----------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------- + */ + +#define CONFIG_SYS_FLASH_BASE 0x00000000 + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_BASE 0x40020000 +#else +// This is mainly used during relocation in start.S +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */ + +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_SIZE 0x2000000 +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_CFI_NONBLOCK 1 + +#if ENABLE_JFFS +/* JFFS Partition offset set */ +#define CONFIG_SYS_JFFS2_FIRST_BANK 0 +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40 +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Memory bank definitions + * + * Please refer also to Motorola Coldfire user manual - Chapter XXX + * http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf + */ + // Flash: 16 Bit SRAM/ROM standard interface, enabled +#define CONFIG_SYS_BR0_PRELIM 0x00000201 +#define CONFIG_SYS_OR0_PRELIM 0x00000014 + +#define CONFIG_SYS_BR1_PRELIM 0 +#define CONFIG_SYS_OR1_PRELIM 0 + +#define CONFIG_SYS_BR2_PRELIM 0 +#define CONFIG_SYS_OR2_PRELIM 0 + +#define CONFIG_SYS_BR3_PRELIM 0 +#define CONFIG_SYS_OR3_PRELIM 0 + +#define CONFIG_SYS_BR4_PRELIM 0 +#define CONFIG_SYS_OR4_PRELIM 0 + +#define CONFIG_SYS_BR5_PRELIM 0 +#define CONFIG_SYS_OR5_PRELIM 0 + +#define CONFIG_SYS_BR6_PRELIM 0 +#define CONFIG_SYS_OR6_PRELIM 0 + +// SDRAM: 32 Bit (cache-line) size, enabled +#define CONFIG_SYS_BR7_PRELIM 0x00000701 +#define CONFIG_SYS_OR7_PRELIM 0xFF00007C + +/*----------------------------------------------------------------------- + * Port configuration (GPIO) + */ +#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external +GPIO*/ +#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs +(1^=output, 0^=input) */ +#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ +#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART +configuration */ +#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ +#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */ +#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */ + +#endif /* _CONFIG_ASTRO_MCF5373L_H */