28 Apr
2021
28 Apr
'21
5:21 p.m.
Hi!
Dne sreda, 28. april 2021 ob 12:05:55 CEST je Andre Przywara napisal(a):
The "n" factor of the PLL_PERIPH0 clock is using the usual +1 encoding, so we need to adjust the register value before doing the calculation.
This fixes the MMC clock setup on those SoCs, which could be slightly off due to the wrong parent frequency: mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000
Signed-off-by: Andre Przywara andre.przywara@arm.com
Good catch!
Reviewed-by: Jernej Skrabec jernej.skrabec@siol.net
Best regards, Jernej