Hi
I have PQIII-8548 problems in DDR2 configuration. And look for leads. Help will be welcomed.
Details below - Thanks in advance. ++Tal --------------------------------------------------- 1. Board is propeitery board 2. CPU: 8548 (e500 core, v2) 3. SDRAM is DDR2 (not DIMM) 4. DDR is working while using REG file (with JTAG loader). 5. DDR is *not*, working uboot. 6. Burn/Access FLASH is OK L2-SRAM access is OK TLB/LAW - triple check - OK
Few trials so far: 1. using the "spd_sdram" to load the parameters, while removing the "CFG_READ_SPD" and taking the parameters from teh REG file, we get the WRITE ok, and the READ not (using SCOPE to view the signals) 2. In all cases: The D_INIT set in "sdram_cfg_2" *do not* fill the DRAM with the known value of "sdram_data_init".
Rather, after the DRAM is enabled, and we set D_INIT once again. It fills the DRAM with the known value of "sdram_data_init".