On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers.
Is there any public documentation to go with this? I would suggest sprinkling the code with comments to mention the different stages.
BTW, no IO powerdown setting for now?
[...]
+ifeq ($(CONFIG_AM43XX),) +COBJS += ddr.o +COBJS += emif4.o +endif +COBJS-$(CONFIG_AM43XX) += emif4d5.o
Are the steps really different enough to warrant a new file? Can't the changes be handled properly in the code? How has this been handled in OMAPx where DDR3 and LPDDR both are supported?
Regards, Vaibhav