I think I communicated my problem incorrectly. Since this is an optical routing unit there is a lot of data read write that occurs for running applications.
Although the data cache may not contribute significantly to the performance of the boot process, Mr Wei Zhou believes from his past experience that it can help us increase our spead of operation of the kernel, and the applications will run significantly faster. I am new!
My experience with this processor is limited!
My resources are only the frescale documentation and the manual. Any indication of other resources will hugely help.
The simplest way to use data cache the way you appear to want to use it is to use the BATs to map your I/O memory (minimum: >IMMR region) as uncached and the rest of your used memory (flash + >RAM) as cached.
Can any one please sugest an example with BAT mapping? (or point to some resource - I don't mean feed me!). I will try it out
Ifyou don't do that, _everything_ is cached which is
a >Very Bad Thing[tm],
as you found out.
I am experimenting but I have a new shipment of hardware on the way that has 4 channels which mean more data read writes which I believe means I will need the d cache.
I am not aware of anybody having success enabling data cache without BATs/MMUs and successfully maintaining cache coherency by hand (which is what you are hinting at).
Presently I am trying to figure the Registers I can manipulate for: setting up memory Maitain cache coherency while running applications
I know HID0 helps with enabling & disabling locking etc. of I&D caches but I want to figure out configuring the MMU with the BAT registers.
Thank you, Best regards,
Om Vadlapatla
PS:- Please excuse any no conforming netiquet as I will learn very soon.
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